11/30/2020: Last week being Thanksgiving, not as much got done as a regular week. However, I do have recorded videos of all the labs now (Labs 3-6 videos are in this folder, since I did not record them through Zoom). Additionally, all the modified lab code is now in my repository. With all of the labs (tentatively) done, I can now focus my work on our Final Project, which will be updated in the 'Frogger Project' page. However, given the chance, I still am looking for the opportunity to fix the issues I've been having with Lab 6, since I could not make all the modifications to the lab I wanted.
11/20/2020: This week was quite productive. I've uploaded the modified code for labs 3 and 4 to my GitHub repository, and actually had the best time modifying these particular program. However, I'm having a huge issue modifying lab 6 -- I can run and program it unmodified, but have so far not managed to get a bitstream to write with the switch modifications. I'm working on this now so I can use the knowledge for our Frogger project, but may have to find a different way to practice making the screen controllable.
11/12/2020: The past few weeks have been, for the most part, a lot of organizational work. EJ, Sarah, James and I have decided to team up together on our final project, which will be Frogger on an fpga. Additionally, this week Lab 5 was done, although I only had a set of earbud and no speaker. I've added the Lab 5 code to my repository, as well as a recorded video of the lab here. I wasn't able to get zoom recording to work for this lab, which was frustrating. Now that I've gotten a VGA cable and display from Professor Lu as well, I'm able to do the rest of the labs.
11/01/2020: Unfortunately, the past couple of weeks have been mayhem. While I was able to communicate with my group mates about our plans to make progress on the labs, not only did I have pressing midterms and job interviews, but I also had some personal conflicts that ended up taking me away from my work for more time than I anticipated. However, now that the looming deadlines have passed, my group mates and I can focus on DSD far more than was possible previously.
10/16/2020: This week, although there was no class on Tuesday, I met with Professor Lu Wednesday afternoon to pick up the Nexys A7-100T FPGA board for the lab projects for my group. During class we went over the lab briefly, and Friday night we finished Lab 1 after setting up Vivado, creating the decoder and hex counter. Additionally, I've uploaded the code set up that was run to a new CPE-487 repository on GitHub, linked here.
10/09/2020: This week, more group work was settled as we prepared to start working on the labs for CPE-487. All the textbook chapters have been read, and I still need to export my newest notes into my google folder. Additionally, FPGAs and other supplies have begun to be distributed, and our lab group began to make plans to start working together after our next class this upcoming week.
10/01/2020: This week, I continued to read through the textbook, taking notes on and doing some of the exercises out of chapters 9 and 10. Additionally, I compiled PDFs of all my written notes for the class (without worked through examples) so far into one google folder, which can be found here: Notes Drive
9/24/2020: This week, while I was particularly busy with other classwork, I was able to read and take notes through chapter 9 of Free Range VHDL. Additionally, I joined the 'Kevin Lu's #1 Fan Club' group for CPE-487. As a group, we'll be working on FPGA projects together throughout the semester.
9/18/2020: During week 3, I went through several exercises in the book as well as going through some VHDL tutorial on YouTube. Additionally, I read and took notes on Chapters 5, 6, and 7 in the textbook.
09/10/2020: This week mainly focused on coursebook and textbook readings. I read 'The Node is Nonsense' from IEEE, as well as reading and taking notes up through chapter 4 of the textbook. I am now looking into either borrowing or buying my own FPGA board. Additionally, I will be doing some GHDL troubleshooting over the weekend as I may need to reinstall the software to make it work correctly.
09/04/20: I have reviewed the course syllabus and familiarized myself with the course website. Additionally, I created the beginning of this website in order to document my work, both in Digital System Design and my personal projects. I linked my GitHub to the website as well. After this, I read the first chapter of the textbook Free Range VHDL and installed GHDL on my computer.