email:kama@cse.iitm.ac.in
Office : SSB 301, Department of Computer Science and Engineering
IIT Madras
email:patanjali@dsai.iitm.ac.in
Office : 650 , 6th Floor NAC 2 , Wadhwani School of Data Science and Artificial Intelligence
IIT Madras
Lecture Timings
Monday : 5.00 - 5.50 pm
Wednesday : 2.00 - 3.15 pm
Thursday: 3.30 - 4.45 pm
Slots : J slot
Room no : CS15
This course introduces the principles and practices involved in testing modern digital systems and designing them for high testability. The course covers fault modeling, simulation, automatic test pattern generation, and diagnosis of digital circuits, along with design-for-testability (DFT) techniques such as scan chain design. Understanding how testing is integrated into the VLSI design flow to improve reliability, reduce manufacturing defects, and ensure efficient validation of complex digital systems.
M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York, NY, USA: Computer Science Press, 1990.
Quiz I 25% Feb 18
Quiz II 25% Mar 25
EndSem 50% May 9