• Aug 2016— Present: Research Scientist, Intel Labs, Intel, Hillsboro, OR.
• Aug 2011— July 2016: Graduate Research Assistant, School of ECE, Georgia Tech.
• May—Aug 2014: Graduate Intern, Intel Labs, Intel, Hillsboro, OR.
• May—Aug 2013: Graduate Intern, Intel Labs, Intel, Hillsboro, OR.
• Jan 2010—Aug 2011: Faculty Member, Dept of EEE, East West University.
Instructed following course,
Analog IC Design ( EEE 418)
VLSI circuits and Systems (EEE 416)
Engineering Ethics (EEE 404)
Digital Electronics (EEE 205)
Electronics Circuits Fundamentals (EEE 102)
• Jul 2005—Jan 2010: Senior IC Designer Engineer, Power IC Ltd. Designed analog power management ICs (PWM, PFM mode synchronous and asynchronous boost regulators).
Worked for 4 years and 6 months. I've designed several Integrated circuits as Project Leader and as support Design Engineer.
Worked as Test and Characterization Supervisor Engineer
Worked as IC design Trainer in Malaysia
• Aug 2008—Oct 2008: Technical Consultant at MIMOS Berhad Fabrication Facility in Kuala Lumpur, Malaysia.
Worked as Process Integration Consultant.
Supervised Wafer level testing in MIMOS FAB-site test facilty.
Resolved Circuit application issues in MIMOS R&D group.
• Dec 2004—Jul 2005: Faculty Member, Dept of EEE, Islamic University of Technology (IUT)
Conducted Electronics circuits (EEE201) course.