Publications

Journals

• 1. Qingyu Zeng and Yuko Hara-Azumi, "Hardware/Software Codesign of Real-time Intrusion Detection System for Internet of Things Devices," IEEE Internet of Things Journal, 2024. (*accepted)

  2. Mingyu Yang, Tanvir Ahmed, Saya Inagaki, Kazuo Sakiyama, Yang Li, and Yuko Hara-Azumi, "Hardware/Software Cooperative Design against Power Side-channel Attacks on IoT Devices," IEEE Internet of Things Journal, Vol. 11, Issue 9, pp. 16758-16768, May 2024. 

  3. Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, and Yuko Hara-Azumi, "Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis," ACM Transactions on Embedded Computing Systems, vol.22, Issue 5, No.85, pp. 1-17, Sept. 2023.

  4. Ryota Hira, Tomoaki Kitahara, Daiki Miyahara, Yuko Hara-Azumi, Yang Li, and Kazuo Sakiyama, "Software Evaluation for Second Round Candidates in NIST Lightweight Cryptography," Journal of Information Processing, vol.13, pp. 205-219, Mar. 2023.

  5. Go Takatoi, Takeshi Sugawara, Kazuo Sakiyama, Yuko Hara-Azumi, and Yang Li, "The Limits of SEMA on Distinguishing Similar Activation Functions of Embedded Deep Neural Networks," Applied Sciences, vol.12, no.9, Apr. 2022.

  6. Yu Nakayama, Yukito Onodera, Anh Hoang Ngoc Nguyen, and Yuko Hara-Azumi, "Real-Time Resource Allocation in Passive Optical Network for Energy-Efficient Inference at GPU-Based Network Edge," IEEE Internet of Things Journal, vol.9, issue 18, pp.17348-17358, Sept. 2022. 

  7. Mehdi Trabelsi Ajili and Yuko Hara-Azumi, "Multimodal Neural Network Acceleration on a Hybrid CPU-FPGA Architecture: A Case Study," IEEE Access, vol.10, pp.9603-9617, Jan. 2022.

  8. Yu Nakayama, Ryo Yaegashi, Anh Hoang Ngoc Nguyen, and Yuko Hara-Azumi, "Real-Time Reconfiguration of Time-Aware Shaper for ULL Transmission in Dynamic Conditions," IEEE Access, vol.9, pp.115246-115255, Aug. 2021.

  9. Naoki Takeuchi, Masashi Aono, Yuko Hara-Azumi, and Christopher L. Ayala, "A Circuit-Level Amoeba-Inspired SAT Solver," IEEE Transactions on Circuits and Systems II: Express Briefs,  Vol.67, Issue 10, pp.2139-2143, Oct. 2020.

  10. Paniti Achararit, Muhammad Abdullah Hanif, Rachmad Vidya Wicaksana Putra, Muhammad Shafique, and Yuko Hara-Azumi, "APNAS: Accuracy-and-Performance-Aware Neural Architecture Search Considering Neural Hardware Accelerators," IEEE Access, vol.8, pp.165319-165334, Sept. 2020.

  11. Mingyu Yang and Yuko Hara-Azumi, "Implementation of Lightweight eHealth Applications on a Low-Power Embedded Processor," IEEE Access, vol.8, pp.121724-121732, Jul. 2020.

  12. Kaoru Saso and Yuko Hara-Azumi, "Revisiting Simple and Energy-Efficient Embedded Processor Designs Towards the Edge Computing," IEEE Embedded Systems Letters, vol.12, Issue 2, pp.45-49, Jun. 2020.

  13. Anh Hoang Ngoc Nguyen, Masashi Aono, and Yuko Hara-Azumi, "FPGA-based Hardware/Software Co-design of a Bio-inspired SAT Solver," IEEE Access, vol.8, pp.49053-49065, Mar. 2020.

  14. Yuko Hara-Azumi, Naoki Takeuchi, Kazuaki Hara, and Masashi Aono, "Digital Bio-Inspired Satisfiability Solver Leveraging Fluctuations," Japanese Journal of Applied Physics (JJAP), vol.59, no.4, pp.040603:1-040603:10, Mar. 2020.

  15. Hisashi Osawa and Yuko Hara-Azumi, "Approximate Data Reuse-Based Accelerator Design for Embedded Processor," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.24, no.5, pp.56:1-56:25, Aug. 2019.

  16. Sara Ayman Metwalli and Yuko Hara-Azumi, "SSA-AC: Static Significance Analysis for Approximate Computing," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.24, no.3, pp.34:1-34:17, Jun. 2019.

  17. Paniti Achararit, Itaru Hida, Takao Marukame, Tetsuya Asai, and Yuko Hara-Azumi, "Structural Exploration of Stochastic Neural Networks for Severely-Constrained 3D Memristive Devices," IEICE Transactions on Nonlinear Theory and Its Applications, vol.E9-N, no.4, pp.466-478, Oct. 2018.

  18. Takahiro Yamamoto, Ittetsu Taniguchi, Shigeru Yamashita, Hiroyuki Tomiyama, and Yuko Hara-Azumi, "A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers," IEICE Transactions on Fundamentals of Electronics, vol.E100-A, no.7, pp.1496-1499, Jul. 2017.

  19. Noriaki Sakamoto, Tanvir Ahmed, Jason Anderson, and Yuko Hara-Azumi, "SubleqΘ: An Area-Efficient Two-Instruction-Set Computer," IEEE Embedded Systems Letters, vol.9, Issue 2, pp.33-36, Jun. 2017.

  20. Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Transactions on Information and Systems, vol.E97-D, no.11, pp.2827-2834, Nov. 2014.

  21. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs," IPSJ Transactions on System LSI Design Methodology, vol.7, pp.37-45, Feb. 2014.

  22. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, and Yuko Hara-Azumi, "Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips," IEICE Transactions on Fundamentals of Electronics (Special Section on "VLSI Design and CAD Algorithms"), vol.E96-A, no.12, pp.2668-2679, Dec. 2013.

  23. Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Koji Inoue, "Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Transactions on Information and Systems, vol.E96-D, no.10, pp.2268-2271, Oct. 2013.

  24. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks," IPSJ Transactions on System LSI Design Methodology, vol.6, pp.122-126, Aug. 2013.

  25. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Selective Check of Data-Path for Effective Fault Tolerance," IEICE Transactions on Information and Systems (Special Section on "Reconfigurable Systems"), vol.E96-D, no.8, pp.1592-1601, Aug. 2013.

  26. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism," IEICE Transactions on Fundamentals, vol.E93-A, no.2, pp.488-499, Feb. 2010.

  27. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis," Journal of Information Processing, vol.17, pp.242-254, Oct. 2009. (※平成21年度 情報処理学会東海支部学生論文奨励賞)

  28. Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, and Hiroaki Takada, "Embedded System Covalidation with RTOS Model and FPGA," IPSJ Transactions on System LSI Design Methodology, vol.1, pp.126-130, Aug. 2008.

  29. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis," IEICE Transactions on Fundamentals, vol.E90-A, no.12, pp.2853-2862, Dec. 2007.

  30. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Function Call Optimization for Efficient Behavioral Synthesis," IEICE Transactions on Fundamentals, vol.E90-A, no.9, pp.2032-2036, Sep. 2007.

Book Chapters

• 1. Hsuan Hsiao, Jason H. Anderson, and Yuko Hara-Azumi, “Generating Stochastic Bitstreams,” W. Gross and V. Gaudet (eds) Stochastic Computing: Techniques and Applications, Springer, Cham, pp.137-152, Feb. 2019. 

Papers @ International Conferences (Peer-reviewed)

• 1. Gento Hiruma, Mingyu Yang, Yang Li, Kazuo Sakiyama, and Yuko Hara-Azumi, "High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares," International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Porto, Porogul, Jun 19-21, 2024. (*accepted)

  2. Kota Maejima, Takayuki Nishio, Asato Yamazaki, and Yuko Hara-Azumi, "Tram-FL: Routing-based Model Training for Decentralized Federated Learning," IEEE Consumer Communications & Networking Conference (CCNC), pp.1038-1039, Las Vegas, NV, USA, Jan. 6-9, 2024.

  3. Maki Tsukahara, Haruka Hirata, Mingyu Yang, Daiki Miyahara, Yang Li, Yuko Hara-Azumi, and Kazuo Sakiyama, "On the Practical Dependency of Fresh Randomness in AES S-box with Second-Order TI," International Symposium on Computing and Networking (CANDAR), Matsue, Japan, Dec. 1, 2023. (*Best Paper Award)

  4. Naoki Nagamatsu and Yuko Hara-Azumi, "Dynamic Split Computing-Aware Mixed-Precision Quantization for Efficient Deep Edge Intelligence," International Conference on Embedded and Ubiquitous Computing (EUC), pp.2543-2550, Exeter, UK, Nov. 3, 2023.

  5. Keigo Matsumoto, Yoshiaki Inoue, Yuko Hara-Azumi, Kazuki Maruta, Yu Nakayama, Yoshinori Shinohara, Hiroki Ikeda, and Daisuke Hisano, "Implementation of Deep Joint Source-Channel Coding on 5G Systems for Image Transmission," IEEE Vehicular Technology Conference (VTC)-Fall, Hong Kong, 10-13 Oct. 2023.

  6. Asato Yamazaki, Takayuki Nishio, and Yuko Hara-Azumi, "Convergence Improvement by Parameters Exchange in Asynchronous Decentralized Federated Learning for Non-IID Data," Euromicro Conference on Software Engineering and Advanced Applications (SEAA), pp.36-43, Durres, Albania, Sept. 6, 2023.

  7. Keigo Matsumoto, Yoshiaki Inoue, Yuko Hara-Azumi, Kazuki Maruta, Yu Nakayama, and Daisuke Hisano, "Impact of Quantization Noise on CNN-based Joint Source-Channel Coding and Modulation", IEEE Consumer Communications & Networking Conference, pp.465-468, Las Vegas, NV, USA, Jan. 2023.

  8. Yusuke Inuma and Yuko Hara-Azumi, "Hardware SAT Solver-based Area-efficient Accelerator for Autonomous Driving," International Conference on Field-Programmable Technology (ICFPT), pp.1-4, Hong Kong, Dec. 2022.

  9. Shohei Fujimaki, Yoshiaki Inoue, Daisuke Hisano, Kazuki Maruta, Yu Nakayama, and Yuko Hara-Azumi, "A Self-Attention Network for Deep JSCCM: The Design and FPGA Implementation," IEEE Global Communications Conference, pp.6390-6395, Rio de Janeiro, Brazil (Hybrid), Dec. 7th, 2022.

  10. Tomoaki Kitahara, Ryota Hira, Yuko Hara-Azumi, Daiki Miyahara, Yang Li, and Kazuo Sakiyama, "Optimized Software Implementations of Ascon, Grain-128AEAD, and TinyJambu on ARM Cortex-M0," International Workshop on Information and Communication Security, Himeji, Japan, Nov. 2022.

  11. Asato Yamazaki, Takayuki Nishio, and Yuko Hara-Azumi, "Skip & Swap: Efficient Weight Spreading  for Decentralized Machine Learning with Non-IID Data," Work-in-Progress of Asia Pacific Conference on Robot IoT System Development and Platform (APRIS), pp.91-92, Tokyo, Nov. 2nd, 2022. 

  12. Naoya Yokota and Yuko Hara-Azumi, "Gossip Swap SGD: Lightweight Decentralized Machine Learning for Non-homogeneous Data Distribution," International Conference on Intelligent Software Methodologies, Tools, and Techniques, pp.678-689, Kitakyushu, Japan, Sept. 22nd, 2022.

  13. Erina Takeshita, Asahi Sakaguchi, Daisuke Hisano, Yoshiaki Inoue, Kazuki Maruta, Yuko Hara-Azumi, and Yu Nakayama, "Stochastic Image Transmission with CoAP for Extreme Environments," IEEE 95th Vehicular Technology Conference (VTC-Spring) Workshop on ICA, Helsinki, Finland, Jun. 2022.

  14. Ayano Higuchi, Erina Takeshita, Daisuke Hisano, Yoshiaki Inoue, Kazuki Maruta, Takayuki Nishio, Yuko Hara-Azumi, and Yu Nakayama, "Aquatic Fronthaul for Underwater-Ground Communication in 6G Mobile Communications," Workshop 13: Technologies and Proof-of-Concept Activities for 6G 2022 (TPoC6G 2022) in conjunction with IEEE Vehicular Technology Conference (VTC)-Spring, Helsinkim, Finland, Jun. 2022.

  15. Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama and Yuko Hara-Azumi, "Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks," International Symposium on Quality Electronic Design (ISQED), p.1, Apr. 2022.

  16. Phurich Saengthong, Chalermpol Charnsripinyo, Seksan Laitrakun, Yuko Hara-Azumi and Somrudee Deepaisarn, "Thermal-comfort Control using Occupancy Detection and Fuzzy Logic for Air-conditioning Systems," International Conference on Digital Arts, Media and Technology (DAMT), pp.197-202, Jan. 2022.

  17. Rei Kudo, Takeshi Sugawara, Kazuo Sakiyama, Yuko Hara-Azumi, and Yang Li, "Revisiting System Noise in Side-Channel Attacks: Mutual Assistant SCA vs. Genetic Algorithm," Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp.1-6, Dec. 18th, 2021. (*Best Paper Award)

  18. Yoshiaki Inoue, Daisuke Hisano, Kazuki Murata, Yuko Hara-Azumi, and Yu Nakayama, "Deep Joint Source-Channel Coding and Modulation for Underwater Acoustic Communication," IEEE Global Communications Conference, pp.1-7, Dec. 2021.

  19. Taisei Yamana and Yuko Hara-Azumi, "Edge Domain Adaptation through Stepwise Cross-Domain Distillation," Asia Pacific Conference on Robot IoT System Development and Platform (APRIS), pp.1-7, Nov. 30th, 2021.

  20. Naoya Yokota and Yuko Hara-Azumi, "Weight Exchange in Decentralized Distributed Machine Learning for Resource-Constrained IoT Edges," Work-in-Progress of Asia Pacific Conference on Robot IoT System Development and Platform (APRIS), pp.94-95, Nov. 30th, 2021. 

  21. Kosuke Suzuoki, Daisuke Hisano, Kazuki Murata, Yoshiaki Inoue, Yuko Hara-Azumi, and Yu Nakayama, "Space-Time-Domain Adaptive Equalizer Employed Successive Interference Cancellation for Underwater Acoustic Communication," IEEE Vehicular Technology Conference (VTC)-Fall, pp.1-5, Oct. 2021.

  22. Anh Hoang Ngoc Nguyen and Yuko Hara-Azumi, "An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies," International Conference on Field-Programmable Logic and Applications (FPL), pp.179-184, Sept. 2021.

  23. Warnnaphorn Suksuganjana, Seksan Laitrakun, Krit Athikulwongse, Yuko Hara-Azumi, and Somrudee Deepaisarn, "Improved Step Detection with Smartphone Handheld Mode Recognition," International Conference on Knowledge and Smart Technology (KST), pp.55-60, Jan. 21st, 2021.

  24. Hsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, and Jason H. Anderson, "Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 260-265, Jan. 19th 2021. 

  25. Yu Nakayama, Yuko Hara-Azumi, Anh Hoang Ngoc Nguyen, Daisuke Hisano, Yoshiaki Inoue, Takayuki Nishio, and Kazuki Maruta, "Real-Time Routing for Wireless Relay Fronthaul with Vehicle-Mounted Radio Units," IEEE Vehicular Technology Conference (VTC)-Spring, Antwerp, Belgium, pp.1-6, May 25-28th 2020.

  26. Anh Hoang Ngoc Nguyen, Masashi Aono, and Yuko Hara-Azumi, "Amoeba-Inspired Hardware SAT Solver with Effective Feedback Control," International Conference on Field-Programmable Technology (ICFPT), pp.241-246, Tianjin, China, Dec. 11th, 2019.

  27. Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, and Hiroyuki Tomiyama, "Maximum Error-Aware Design of Approximate Array Multipliers," International SoC Design Conference (ISOCC), pp.73-74, Jeju, Korea, Oct. 7th, 2019.

  28. Kazuaki Hara, Naoki Takeuchi, Masashi Aono, and Yuko Hara-Azumi, "Amoeba-Inspired Stochastic Hardware SAT Solver," International Symposium on Quality Electronic Design (ISQED), pp.151-156, Santa Clara, CA, USA, Mar. 6th, 2019.

  29. Kaoru Saso and Yuko Hara-Azumi, "Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices," International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.93-96, Milan, Italy, Jul. 10th, 2018. 

  30. Hisashi Osawa and Yuko Hara-Azumi, "Approximate Data Reuse-based Processor: A Case Study on Image Compression," Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), pp.32-40, Seoul, Korea, Oct. 19th, 2017. 

  31. Minato Yokota, Kaoru Saso, and Yuko Hara-Azumi, "One-Instruction Set Computer-based Multicore Processors for Energy-Efficient Streaming Data Processing," International Symposium on Rapid System Prototyping (RSP), pp.71-77, Seoul, Korea, Oct. 19th, 2017.

  32. Goragod Pongthanisorn, Natavut Kwankeo, Kamol Kaemarungsi, and Yuko Hara-Azumi, "A Software Level Energy Efficient Algorithm on Real-Time Embedded System based on FreeRTOS," International Conference on Embedded Systems and Intelligent Technology (ICESIT2017), Bangkok, Thailand, Aug. 3rd, 2017

  33. S Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, and Jason Anderson, "CGRA-ME: A Unified Framework for CGRA Modelling and Exploration," International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.184-189, Seattle, WA, Jul. 12th, 2017.

  34. Takahiro Yamamoto, Ittetsu Taniguchi, Shigeru Yamashita, Hiroyuki Tomiyama, and Yuko Hara-Azumi, "A Systematic Methodology for Design and Analysis of Approximate Array Multipliers,"Asia Pacific Conference on Circuits and Systems (APCCAS), pp.352-354, Jeju, Korea, Oct. 27th, 2016.

  35. Jason Anderson, Yuko Hara-Azumi, and Shigeru Yamashita, "Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy," Design, Automation & Test in Europe (DATE), pp.1550-1555, Dresden, Germany, Mar. 17th, 2016.

  36. Tanvir Ahmed, Noriaki Sakamoto, Jason Anderson, and Yuko Hara-Azumi, "Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC," International Conference on Embedded and Ubiquitous Computing (EUC), pp.114-123, Porto, Portugal, Oct. 22nd, 2015.

  37. Tanvir Ahmed and Yuko Hara-Azumi, "Timing Speculation-Aware Instruction Set Extension for Resource-Constrained Embedded Systems," International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.30-34, Toronto, Canada, Jul. 27th, 2015.

  38. Takumi Tsuzuki, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.199-204, Yilan, Taiwan, Mar. 16th, 2015.

  39. Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, and Jason Anderson, "Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis," Design, Automation & Test in Europe (DATE), pp.31-36, Grenoble, France, Mar. 10th, 2015.

  40. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Better-than-DMR Techniques for Yield Improvement," International Symposium on Field-Programmable Custom Computing Machines (FCCM), p.34, Boston, MA, USA, May 12th, 2014.

  41. Yuko Hara-Azumi, Masaya Kunimoto, and Yasuhiko Nakashima, "Emulator-Oriented Tiny Processors for Unreliable Post-Silicon Devices: A Case Study," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.85-90, Singapore, Jan. 21st, 2014.

  42. Takuya Azumi, Yasaman Samei Syahkal, Yuko Hara-Azumi, Hiroshi Oyama, and Rainer Dömer, "TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component," International Embedded Systems Symposium (IESS), pp.1-13, Paderborn, Germany, Jun. 17th, 2013.

  43. Ryoya Sobue, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Partial Controller Retiming in High-Level Synthesis," Electronic System Level Synthesis Conference (ESLsyn), pp.10-15, Austin, TX, USA, May 31st, 2013.

  44. Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, and Mehdi Tahoori, "Instruction-Set Extension under Process Variation and Aging Effects," Design, Automation & Test in Europe (DATE), pp.182-187, Grenoble, France, Mar. 19th, 2013.

  45. Yuko Hara-Azumi and Hiroyuki Tomiyama, "Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation," International Symposium on Quality Electronic Design (ISQED), pp.518-523, Santa Clara, CA, USA, Mar. 5th, 2013.

  46. Yuko Hara-Azumi, Takuya Azumi, and Nikil D. Dutt, "VISA Synthesis: Variation-Aware Instruction Set Architecture Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.243-248, Yokohama, Japan, Jan. 23rd, 2013.

  47. Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, and Shigeru Yamashita, "A Redundant Wire Addition Method for Patchable Accelerator," International Conference on Electronics, Circuits, and Systems (ICECS), pp.552-555, Seville, Spain, Dec. 2012.

  48. Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, and Koji Inoue, "Task Mapping Techniques for Embedded Many-core SoCs," International SoC Design Conference (ISOCC), pp.204-207, Jeju, Korea, Nov. 2012.

  49. Yuko Hara-Azumi,  Toshinobu Matsuba,  Hiroyuki Tomiyama,  Shinya Honda,  and Hiroaki Takada, "Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis," International Conference on Embedded Software and Systems (ICESS), pp.1534-1540, Liverpool, UK, Jun. 26th, 2012.

  50. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, and Nikil D. Dutt, "High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.414-419, Oita, Japan, Mar. 9th, 2012.

  51. Daiki Tsuruta, Masayuki Wakizaka, Yuko Hara-Azumi, and Shigeru Yamashita, "A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.396-401, Oita, Japan, Mar. 2012.

  52. Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, and Shigeru Yamashita, "Bit Selective SAD and Its Evaluation," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.22-27, Oita, Japan, Mar. 2012.

  53. Yuko Hara-Azumi and Hiroyuki Tomiyama, "Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.251-256, Sydney, Australia, Feb. 2012.

  54. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.13-18, Taipei, Taiwan, Oct. 2010. 

  55. Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis," International Symposium on Electronic Design, Test & Applications (DELTA), pp.87-92, Ho Chi Minh City, Vietnam, Jan. 2010. 

  56. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Behavioral Partitioning with Exploiting Function-Level Parallelism," International SoC Design Conference (ISOCC), pp.121-124, Busan, Korea, Nov. 2008.

  57. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis," International Symposium on Circuits and Systems (ISCAS), pp.1192-1195, Seattle, WA, USA, May 2008.

  58. Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, and Hiroaki Takada, "Hardware/Software Covalidation with FPGA and RTOS Model," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.488-494, Sapporo, Japan, Oct. 2007.

  59. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda , Hiroaki Takada, and Katsuya Ishii, "Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study," International Conference on Embedded Software and Systems (ICESS), pp.261-270, Daegu, Korea, May 2007.

  60. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Complexity-Constrained Partitioning of Sequential Programs for Efficient Behavioral Synthesis," ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.365-370, Stresa, Italy, Mar. 2007.

  61. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Function Call Optimization in Behavioral Synthesis," Euromicro Symposium on Digital System Design (DSD), pp.522-529, Cavtat, Croatia, Aug. 2006.

Invited talks @ International Conferences

• 1. Yuko Hara-Azumi, "Highly-Scalable and Flexible Multicore Processors with Limited ISAs," 18th International Forum on MPSoC for Software-defined Hardware (MPSoC), Snowbird, UT, USA, Aug. 2nd, 2018.

  2. Yuko Hara-Azumi, "Energy-Efficient Multicore Processor for Large Stream Data in IoT Systems," 17th International Forum on MPSoC for Software-defined Hardware (MPSoC), Annecy, France, Jul. 4th, 2017.

  3. Yuko Hara-Azumi, Hisashi Osawa, and Tanvir Ahmed, "Architectural Approach on Approximate Computing for Media Processing," International Symposium on Nonlinear Theory and Its Applications (NOLTA), p.397, Yugawara, Nov. 29th, 2016.

  4. Yuko Hara-Azumi, "Area-Efficient Error Detection and Recovery for Dependable Embedded Systems," 16th International Forum on MPSoC for Software-defined Hardware (MPSoC), Nara, Japan, Jul. 14th, 2016.

  5. Yuko Hara-Azumi, Tanvir Ahmed, Takuya Azumi, and Nikil D. Dutt, "Instruction-Set Extension of Embedded Microprocessor for Timing Speculation," International Conference on Integrated Circuits, Design, and Verification (ICDV), pp.67-72, Ho Chi Minh City, Vietnam, Aug. 11th, 2015.

  6. Yuko Hara-Azumi, "Partially-Programmable Circuit: New Flexible Method for Fault-Tolerance Improvement and Its Application," Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, Jun. 10th, 2015.

  7. Yuko Hara-Azumi, Toshihiko Kamata, Ittetsu Taniguchi, and Hiroyuki Tomiyama, "Yield-Aware Allocation and Binding of Partially-Programmable Functional Units," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp.729-732, Phuket, Thailand, Jul. 2nd, 2014.

  8. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, and Yuko Hara-Azumi, "A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidics Biochips," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.199-204, Yokohama, Japan, Jan. 23rd, 2013.

  9. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Nikil Dutt, "Towards Practical High-Level Synthesis From Large Behavioral Descriptions," International SoC Design Conference (ISOCC), pp.71-74, Incheon, Korea, Nov. 2010.

Posters (with Oral Presentation) @ International Conferences/Symposia/Workshops 

• 1. Tanvir Ahmed and Yuko Hara-Azumi, "A Highly Efficient Reinforcement Learning Based DFG Mapping Method on CGRA," Work-in-Progress (WiP) of Design Automation Conference (DAC), San Francisco, CA, USA, July 2023. [Peer-reviewed, Poster Presentation]

  2. Mingyu Yang and Yuko Hara-Azumi, "Co-Design of Lightweight eHealth Applications on a IoT Egde Processor," Ph.D. Forum of Design, Automation & Test in Europe (DATE), Antwarp, Belgium, Apr. 1st, 2023. [Not peer-reviewed, Poster Presentation]. 

  3. Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama and Yuko Hara-Azumi, "Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis," International Symposium on Field-Programmable Gate Arrays (ISFPGA), p.52, Feb. 13th, 2023. [Peer-reviewed, Poster Presentation]

  4. Anh Nguyen and Yuko Hara-Azumi, "Amoeba-inspired System Controller on IoT Edge," Ph.D. Forum of Design, Automation & Test in Europe (DATE), Virtual, Feb. 1st, 2021. [Not peer-reviewed, Poster Presentation]. 

  5. Mingyu Yang and Yuko Hara-Azumi, "Implementation and Evaluation of an Embedded Processor for Lightweight IoT eHealth," University Booth of Design, Automation & Test in Europe (DATE), Virtual, Mar. 11-12th, 2020. [Not peer-reviewed, Poster Presentation]. 

  6. Mehdi Trabelsi Ajili and Yuko Hara-Azumi, "FPGA Acceleration of a Multimodal Neural Network," University Booth of Design, Automation & Test in Europe (DATE), Virtual, Mar. 11-12th, 2020. [Not peer-reviewed, Poster Presentation].

  7. Anh Hoang Ngoc Nguyen, Masashi Aono, and Yuko Hara-Azumi, "FPGA-Based Amoeba-Inspired SAT Solver for Cyber-Physical Systems," Work-in-Progress of International Conference on Cyber-Physical Systems (ICCPS), pp.316-317, Montreal, Canada, Apr. 16th, 2019. [Peer-reviewed, Poster Presentation]

  8. Sara Metwalli and Yuko Hara-Azumi, "SEA-AC: Symbolic Execution-based Analysis towards Approximate Computing," ACM Student Research Competition (SRC) in conjunction with the 51st IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka, Oct. 22nd, 2018. [Peer-reviewed, Poster Presentation]

  9. Kaoru Saso, Jing Yuan Zhao, and Yuko Hara-Azumi, "OISC Multicore Stencil Processor: One Instruction-Set Computer-Based Multicore Processor for Stencil Computing," University Booth of Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 20th-22nd, 2018 [Not peer-reviewed, Poster Presentation & Demonstration].

  10. Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, and Yuko Hara-Azumi, "Systematic Design of Approximate Array Multipliers with Different Accuracy," International Workshop on Highly Efficient Neural Networks Design (HENND), Seoul, Korea, Oct. 20th, 2017. [Peer-reviewed, Poster Presentation]

  11. Kazuaki Hara and Yuko Hara-Azumi, "A Scalable FPGA Implementation of Amoeba-SAT Solver," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]

  12. Fransiscus Marcel Satria and Yuko Hara-Azumi, "Efficient Data Clustering by Architectural Perforation," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]

  13. Anh Hoang Ngoc Nguyen and Yuko Hara-Azumi, "Exploration of Hardware-Implementation-Aware Amoeba-SAT Solver," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]

  14. Goragod Pongthanisorn, Natavut Kwankeo, Kamol Kaemarungsi, and Yuko Hara-Azumi, "Analysis of Energy Consumption Mode from Various Embedded System Application," International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES 2017), Chonburi Beach, Thailand, May 9th, 2017. [Peer-reviewed, Poster Presentation]

  15. Yuko Hara-Azumi, "Area-Efficient Error Recovery for Dependable Embedded Systems," EDA workshop in conjunction with ASP-DAC 2017 TPC Meeting, Hong Kong, Aug. 29th, 2016. [Not peer-reviewed, Oral Presentation]

  16. Kazuki Zenba, Tanvir Ahmed, and Yuko Hara-Azumi, "Fast and Simple Netlist-level Fault-Injection Framework on FPGA," IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIX, Yokohama, Apr. 21st-22nd, 2016. [Peer-reviewed, Poster Presentation]

  17. Noriaki Sakamoto, Tanvir Ahmed, Jason H. Anderson and Yuko Hara-Azumi, "Design Space Exploration of Flexible Heterogeneous Dual-Core Processor using MIPS and Extended OISC: A Case Study," 1st Workshop on Resource Awareness and Application Auto-tuning in Adaptive and Heterogeneous Computing (RES4ANT) in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 18th, 2016. [Peer-reviewed, Poster Presentation]

  18. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Novel Area-Efficient Technique for Yield Improvement," Electronic System-Level Design towards Heterogeneous Computing in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 28th, 2014. [Not peer-Reviewed, Poster Presentation]

  19. Takuya Azumi, Yuko Hara-Azumi, and Rainer Dömer, "Virtual Platform Generation Using TECS Software Component and SCE," Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 16th, 2012. [Peer-reviewed, Poster Presentation]

  20. Takuya Azumi, Yuko Hara-Azumi, Shinya Honda, and Hiroaki Takada, "Software Component-Based HW/SW Cosimulation Framework: A Case Study," Work-In-Progress of Real-Time and Embedded Technology and Applications Symposium (RTAS), Chicago, IL, USA, Apr. 2011. [Peer-reviewed, Oral & Poster Presentation]

  21. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "The CHStone Benchmark Suite for Practical C-Based High-Level Synthesis," High-Level Synthesis: Next Step to Efficient ESL Design in conjunction with Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2009. [Not peer-reviewed, Oral Presentation]

  22. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "The CHStone Benchmark Suite for Practical C-Based High-Level Synthesis," High-Level Synthesis: Back to the Future in conjunction with Design Automation Conference (DAC), Anaheim, CA, USA, Jun. 2008. [Not peer-reviewed, Poster Presentation]

  23. Yuko Hara, "Efficient Behavioral Synthesis from Large Sequential Programs," Student Forum at Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, Jan. 2008. [Peer-reviewed, Poster Presentation]

Domestic Symposia (Peer-reviewed)

• 1. Paniti Achararit, Itaru Hida, Tetsuya Asai, and Yuko Hara-Azumi, "On the Neuromorphic 3D Devices for Locally-Connected Convolutional Neural Network," The 28th Annual Conference of the Japanese Neural Network Society, Okinawa, Oct. 26th, 2018.

  2. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子,  "改良型配列型近似乗算器の設計と解析," 回路とシステムワークショップ, pp.13-18, 北九州, 2017年5月11日.

  3. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子, "配列型近似乗算器の設計と解析," 回路とシステムワークショップ, pp.237-242, 北九州, 2016年5月13日. 

  4. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, "動作合成における関数呼出しの最適化," 電子情報通信学会 第19回 回路とシステム軽井沢ワークショップ論文集, pp.607-612, 軽井沢, 2006年4月.

Domestic Symposia (Not peer-reviewed)

• 1. 一岡 知佑, タンビア アーメド, 原 祐子, "eFPGAを用いた組込みプロセッサのIP保護," ハードウェアセキュリティ研究会，那覇，2024年3月2日.

  2. 楊 明宇, 比留間 絃斗, 崎山 一男, 李 陽, 原 祐子, "コンポーザブルセキュリティによる暗号回路の高位合成," ハードウェアセキュリティ研究会，沖縄県那覇市，2024年3月2日.

  3. 角 颯太, 楊 明宇, 原 祐子, "故障注入攻撃耐性を強化した擬似乱数生成器の設計," ハードウェアセキュリティ研究会，那覇，2024年3月1日.

  4. 卯木 あゆ美, 原 祐子, "Graph Neural Networkを用いた組み込みプロセッサ拡張," VLSI設計技術研究会，那覇，2024年2月29日.

  5. Qingyu Zeng, Yuko Hara, "FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection," リコンフィギャラブルシステム研究会，神奈川県川崎市， 2024年1月30日.

  6. 原田 優咲, 塚原 麻輝, 宮原 大輝, 李 陽, 原 祐子, 崎山 一男, "TI-AESに使用する擬似乱数生成器の物理安全性への影響," 暗号と情報セキュリティシンポジウム (SCIS), 長崎, 2024年1月24日

  7. 松本 啓吾, 森 智香, 井上 文彰, 原 祐子, 丸田 一輝, 中山 悠, 篠原 義典, 池田 博樹, 久野 大介, "Deep Joint Source-Channel Coding 方式とローカル5G システムの接続検証," コミュニケーションシステム研究会, 鹿児島, 2024年1月12日

  8. 曾 慶宇, 原 祐子, "IoT Network Security Enhancement: Leveraging Deep Learning for Intrusion Detection and Addressing Data Imbalance," 第203回システムとLSIの設計技術研究発表会，京都，2023年11月7日．（※最優秀賞受賞）

  9. 山﨑 朝斗, 西尾 理志, 原 祐子, "不均一なデータ分布下での効果的な非同期型分散学習法," 第203回システムとLSIの設計技術研究発表会，京都，2023年11月7日．（※最優秀賞受賞）

  10. Ruichen Ma, Yuko Hara-Azumi, "Hardware-Aware Joint Source-Channel Coding and Modulation Design and its FPGA Implementation," 第203回システムとLSIの設計技術研究発表会，京都，2023年11月7日．（※主査特別賞受賞）

  11. 原田 優咲, 塚原 麻輝, 宮原 大輝, 李 陽, 原 祐子, 崎山 一男, "擬似乱数生成器がTI-AESの一様性に与える影響に関する基礎実験," IEICE2023年ソサイエティ大会, 名古屋, 2023年9月.

  12. 山本 龍之介, 松本 啓吾, 井上 文彰, 原 祐子, 丸田 一輝, 中山 悠, 久野 大介, "5Gセルラー通信に応用可能な情報源通信路深層結合符号化における学習モデルの影響評価," IEICE2023年ソサイエティ大会, 名古屋, 2023年9月.

  13. 稲垣 沙耶，楊 明宇, 李 陽, 﨑山 一男, 原 祐子, "電力サイドチャネル攻撃に対して堅牢なARX型暗号回路の高位合成," 暗号と情報セキュリティシンポジウム (SCIS), 北九州, 2023年1月26日.

  14. 天野 龍乃如，崎山 一男，原 祐子，李 陽，"シミュレーションによるニューラルネットワークの乗算に対するサイドチャネル攻撃の考察," 暗号と情報セキュリティシンポジウム (SCIS), 北九州, 2023年1月26日.

  15. Enhao Xu, Takeshi Sugawara, Kazuo Sakiyama, Yuko Hara-Azumi, Yang Li, "Attention-Based Non-Profiled SCA on ASCAD Database," 暗号と情報セキュリティシンポジウム (SCIS), 北九州, 2023年1月26日.

  16. 西澤 慧悟，崎山 一男，原 祐子，李 陽，"相互補助相関電力解析の正解鍵順位と鍵復元率の調査," 暗号と情報セキュリティシンポジウム (SCIS), 北九州, 2023年1月25日.

  17. 小野 悠真，Paniti Archararit，原 祐子, "敵対的攻撃に対して頑健かつ軽量な深層学習モデルの自動探索," 暗号と情報セキュリティシンポジウム (SCIS), 北九州, 2023年1月24日.

  18. 佐々木 智大, 原 祐子, "高位合成を用いたGentleman-Sande型NTTの高速化," 第199回システムとLSIの設計技術研究発表会，2022-SLDM-199(7), 京都, 2022年11月11日．

  19. 永松 直樹, 原 祐子, "Neural Architecture SearchによるSplit Inferenceの効率化," 第199回システムとLSIの設計技術研究発表会，2022-SLDM-199(2), 京都, 2022年11月11日．(※SLDM研究発表会WIP最優秀賞)

  20. 楊 明宇, Tanvir Ahmed, 稲垣 沙耶, 﨑山 一男, 李 陽, 原 祐子, "ハードウェア/ソフトウェア協調設計によるIoTデバイスの電力解析攻撃対策," 第199回システムとLSIの設計技術研究発表会，2022-SLDM-199(4), 京都, 2022年11月11日．

  21. 原 祐子，"組込みマイクロプロセッサにおけるハードウェアセキュリティ," 電子情報通信学会Webinarテクノロジートレンドシリーズ，オンライン，2022年6月21日.（※講演）

  22. 楊 明宇, 﨑山 一男, 李 陽, 原 祐子, "低電力組込みプロセッサの電力解析攻撃耐性に関する検討,"LSIとシステムのワークショップ，東京，2022年5月17日. [ポスター発表]

  23. 井沼 佑亮, 原 祐子, "AmoebaSATを用いた効率的な自動運転アクセラレータ," VLSI設計技術研究会 (VLD), vol. 121, no. 412, VLD2021-90, pp. 75-80, オンライン, 2022年3月7日．

  24. 北原 知明, 日良 僚太, 原 祐子, 宮原 大輝, 李 陽, 崎山 一男, "NIST軽量暗号最終候補におけるソフトウェア実装性能の評価," 暗号と情報セキュリティシンポジウム (SCIS), 大阪/オンライン, 2022年1月21日.

  25. 渡辺 陸, 楊 明宇, 原 祐子, 﨑山 一男, 李 陽, "RISC−VとSubRISC+におけるLED暗号のBitslice実装の評価," 暗号と情報セキュリティシンポジウム (SCIS), 大阪/オンライン, 2022年1月18日.

  26. 楊 明宇, 卯木 あゆ美, 李 陽, 﨑山 一男, 原 祐子, "少命令セット組込みプロセッサにおけるARX型暗号アルゴリズムの実装と評価," 暗号と情報セキュリティシンポジウム (SCIS), 大阪/オンライン, 2022年1月18日.

  27. 原 祐子, "次世代IoTに向けた低電力プロセッサSubRISC+," IEEE Circuits and Systems (CAS) Society Kansai Chapter, 2021年11月12日. (※招待講演) 

  28. 丸田 一輝, 中山 悠, 久野 大介, 井上 文彰, 原 祐子, "超高遅延・ロス環境における画像内価値に基づくブロック確率転送," IEICE2021年ソサイエティ大会, オンライン, 2021年9月14日.

  29. 北原 知明, 日良 僚太, 原 祐子, 李 陽, 崎山一男, "NIST軽量暗号最終候補のAD長と平文長に対するレイテンシの測定," IEICE2021年ソサイエティ大会, オンライン, 2021年9月14日.

  30. 伊藤 千夏, 原 祐子, 崎山 一男, 李 陽, "GIFT暗号を用いたソフトウェア閾値法の実装," IEICE2021年ソサイエティ大会, オンライン, 2021年9月14日.

  31. 井上 文彰, 久野 大介, 丸田 一輝, 原 祐子, 中山 悠, "深層学習に基づく一括符号化変調を用いた水中音響画像伝送," IEICE2021年ソサイエティ大会, オンライン, 2021年9月16日.

  32. 鈴置 皓介, 久野 大介, 丸田 一輝, 井上 文彰, 原 祐子, 中山悠, "逐次干渉除去を用いた時空間適応等化器の水中音響通信への応用," IEICE2021年ソサイエティ大会, オンライン, 2021年9月16日.

  33. 原 祐子, "IoTエッジコンピューティングに向けた小型低電力プロセッサSubRISC+," 情報処理学会 SLDM研究会 DAシンポジウム, オンライン, 2021年9月1日. (※招待講演)

  34. 坂口 朝陽, 丸田 一輝, 井上 文彰, 中原 睦貴, 久野 大介, 原 祐子, 中山 悠, "超高遅延・ロス環境での遠隔物体検出のための確率的画像転送法," 第20回情報科学技術フォーラム (FIT), オンライン, 2021年8月26日. 

  35. 原 祐子, "IoTエッジ端末向け小型低電力プロセッサSubRISC+," 情報処理学会 組込みシステム研究会, オンライン, 2021年6月28日. (※招待講演)

  36. 高樋 剛, 菅原 健, 﨑山 一男, 原 祐子, 李 陽, "ディープニュラルネットワークの活性化関数 に対する単純電磁波解析," 情報セキュリティ研究会, オンライン, 2021年5月19日. (※招待講演)

  37. 原 祐子, "IoTエッジ端末向け小型低電力プロセッサ," RISC-V Days Tokyo Spring, 2021年4月23日. (※招待講演)

  38. 八重樫 遼, 原 祐子, Anh Hoang Ngoc Nguyen, 中山 悠, "FPGA-SATソルバを用いたGate Control Listの高速アップデート法", 電子情報通信学会総合大会, オンライン, 2021年3月10日.

  39. 稲垣 沙耶, 楊 明宇, 李 陽, 崎山 一男, 原 祐子, "高位合成による軽量暗号ChaskeyのFPGA実装およびサイドチャネル攻撃耐性の評価," ハードウェアセキュリティ研究会, VLD2020-79, HWS2020-54 (2021-03), pp.61-66, オンライン, 2021年3月4日.

  40. 小名木 さゆり, 原 祐子, "低消費エネルギーな組み込みマルチコアプロセッサの設計空間探索," VLSI設計技術研究会, VLD2020-86, HWS2020-61 (2021-03), pp.102-107, オンライン, 2021年3月4日. 

  41. Go Takatoi, Takeshi Sugawara, Kazuo Sakiyama, Yuko Hara-Azumi, Yang Li, "Pushing the Limits of Simple Electromagnetic Analysis Against Similar Activation Functions," 暗号と情報セキュリティシンポジウム (SCIS), オンライン, 2021年1月20日.

  42. 工藤 黎, 菅原 健, 崎山 一男, 原 祐子, 李 陽, "サイドチャネル攻撃の並列実装におけるシステムノイズの評価: 遺伝的アルゴリズムとの比較," 暗号と情報セキュリティシンポジウム (SCIS), オンライン, 2021年1月20日.

  43. 日良 僚太, 李 陽, 原 祐子, 崎山 一男, "NIST軽量暗号第2ラウンド候補のソフトウェア実装に向けた調査," 暗号と情報セキュリティシンポジウム (SCIS), オンライン, 2021年1月20日.

  44. 日良 僚太, 李 陽, 原 祐子, 崎山 一男, “NIST軽量暗号の第2ラウンド候補の軽量実装に向けた分類と比較,” IEICE2020年ソサイエティ大会, オンライン, 2020年9月17日.

  45. 君島 舜, フランシスクス マルセル サトリア, 原 祐子, "組込みシステムにおける近似計算を用いたデータクラスタリング高速化," VLSI設計技術研究会 (VLD) 信学技報, vol.118, no.457, VLD2018-129, pp. 217-222, 那覇, 2019年3月1日. 

  46. 小名木 さゆり, 佐宗 馨, 原 祐子, "IoTエッジコンピューティングに向けた省エネルギー・小型なマルチコアプロセッサ," VLSI設計技術研究会 (VLD) 信学技報, vol.118, no.457, VLD2018-128, pp. 211-216, 那覇, 2019年3月1日. 

  47. 原 祐子, "近似データ再利用に基づく組込みシステムのアクセラレータ設計," 2018年電子情報通信学会ソサイエティ大会, pp.SS28-SS29, 金沢, 2018年9月14日. (※招待講演)

  48. Anh Hoang Ngoc Nguyen,  Masashi Aono, and Yuko Hara-Azumi, "Amoeba-inspired SAT Solvers on FPGA through High Level Synthesis," VLSI設計技術研究会 (VLD) 信学技報, vol.117, no.455, VLD2017-93, pp.25-30, 那覇, 2018年2月28日.

  49. Sara Ayman Metwalli and Yuko Hara-Azumi, "Systematic Analysis Framework of Variables Significance towards Approximate Computing,"VLSI設計技術研究会 (VLD) 信学技報, vol.117, no.455, VLD2017-94, pp.31-36, 那覇, 2018年2月28日.

  50. 原 祐子, "高位合成の近年の研究動向 ～デバイス技術とアプリケーション多様化～," 回路とシステムワークショップ, p.19, 北九州, 2017年5月11日. (※招待講演)

  51. 大澤 永始，Tanvir Ahmed，原 祐子，"Approximate Computingに基づいたデータ再利用型組込みプロセッサ," LSIとシステムのワークショップ，東京，2016年5月17日. [ポスター発表]

  52. 春日井 貴通，山下 茂，原 祐子，"Partially-Programmable Circuit を用いた遅延故障の回避手法," 情報処理学会 組込み技術とネットワークに関するワークショップ （ETNET）, vol.2016-EMB-40, no.25, pp.1-6, 五島, 2016年3月25日.

  53. 原 祐子, "国際会議採択に向けて ~留学・プログラム委員の経験から~," 情報処理学会 デザインガイア, p.69, 長崎, 2015年12月2日. (※招待講演)

  54. 酒本 典明, タンビア アーメド, ジェイソン アンダーソン, 原 祐子, "単一命令セットコンピュータの拡張とその評価," VLSI設計技術研究会 (VLD), pp.19-24, 小樽, 2015年6月17日.

  55. 原 祐子, "システムレベル設計の研究動向," LSIとシステムのワークショップ ２０１５, 北九州, 2015年5月13日. (※招待講演)

  56. 杉山 翔一郎, タンビア アーメド, 原 祐子, "ルックアップテーブルを用いたapproximate computing向けアーキテクチャの実装と評価," VLSI設計技術研究会 (VLD), pp.171-176, 那覇, 2015年3月4日．

  57. 谷口 一徹, 甲斐田 純也, 稗田 拓路, 原 祐子, 冨山 宏之,"数理計画アプローチによる動的タスク切り替えを考慮した組込みメニーコアSoC向けタスクマッピング," 計測自動制御学会 システム・情報部門 学術講演会 (SICE-SSI), p.1131, 岡山, 2014年11月. 

  58. 原 祐子, "組込みシステム上流設計の研究動向について（アーキテクチャとEDA）," 第90回STRJ-ERD会合, 2014年9月26日. (※招待講演)

  59. 都築 匠, 原 祐子, 山下 茂, 中島 康彦, "PPCにおけるLUT挿入位置最適化の定量的評価," 情報処理学会 DAシンポジウム, pp.67-72, 下呂, 2014年8月28日．

  60. 祖父江 亮哉, 原 祐子, 谷口 一徹, 冨山宏之, "高位合成におけるマルチプレクサの遅延の削減手法," 情報処理学会 組込み技術とネットワークに関するワークショップ （ETNET）, 石垣島, 2014年3月15日.

  61. 祖父江 亮哉, 原 祐子, 谷口 一徹, 冨山宏之, "高位合成における制御回路の構成方法の定量的評価," 情報処理学会 デザインガイア, VLD2013-65, Vol.113, No.320, pp.257-262, 鹿児島, 2013年11月29日.

  62. 早苗 駿一, 原 祐子, 山下 茂, 中島 康彦, "PPCに基づく高歩留まり回路の発見的設計手法," 情報処理学会 デザインガイア, VLD2013-65, Vol.113, No.320, pp.27-32, 鹿児島, 2013年11月27日. (※第163回SLDM研究会 優秀発表学生賞)

  63. 早苗 駿一, 原 祐子, 山下 茂, 中島 康彦, "Partially-Programmable Circuit の歩留まり向上のためのLUT 最適化手法," 情報処理学会 DAシンポジウム, pp.27-32, 下呂, 2013年8月21日．

  64. 國本 将也, 原 祐子, 中島 康彦, "永久故障回避のための等価命令列置換手法," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, Vol.113, No.169, CPSY2013-30, pp.121-126, 北九州, 2013年7-8月. (※CPSY 優秀若手講演賞)

  65. 藤原 知広, 姚 駿, 原 祐子, 中島 康彦, "リング型アレイアクセラレータのマクロパイプライン化による性能見積もり," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.14, pp.1-6, 北九州, 2013年7-8月.

  66. 林 大地, 関 賀, 原 祐子, 姚 駿, 中島 康彦, "メモリ分散型アレイアクセラレータの浮動小数点演算に関する性能考察," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.8, pp.1-6, 北九州, 2013年7-8月.

  67. 稲垣 慶和, 原 祐子, 姚 駿, 中島 康彦, "リング型アレイアクセラレータ向け演算ライブラリの実装と性能評価," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.1, pp.1-6, 北九州, 2013年7-8月.

  68. Hao Xu, Yuko Hara-Azumi, and Yasuhiko Nakashima, "Comparison of Emulation-Oriented 8-bit ISA with 6502 ISA for an ARM Emulator," 情報処理学会 ARC研究会, 2013-ARC-204 No.9, pp.1-6, 和歌山, 2013年3月．

  69. 祖父江 亮哉, 原 祐子, 稗田 拓路, 谷口 一徹, 冨山 宏之, "クロック周波数向上のための動作合成におけるコントローラ設計手法," 情報処理学会 デザインガイア, 2012-SLDM-158, No.20, pp.1-6, 福岡, 2012年11月27日. (※第158回SLDM研究会 優秀発表学生賞)

  70. Yuko Hara-Azumi，Takuya Azumi，and Nikil D. Dutt, "Instruction Set Architecture Synthesis Exploiting Process Variation," 情報処理学会 DAシンポジウム , pp.127-132, 下呂, 2012年8月.

  71. 甲斐田 純也，稗田 拓路，谷口 一徹，冨山 宏之，原 祐子，井上 弘士, "組込みメニーコア向けタスクマッピング手法," 情報処理学会 DAシンポジウム, pp.67-72, 下呂, 2012年8月.

  72. 鶴田 大貴，安積(原) 祐子，山下 茂, "リソースの再利用による実装面積を考慮した耐故障化高位合成手法," 情報処理学会 DAシンポジウム, pp.15-20, 下呂, 2011年8月.

  73. Yuko Hara-Azumi, Hiroyuki Tomiyama, Takuya Azumi, Shigeru Yamashita, Nikil D. Dutt, and Hiroaki Takada, "Soft Error-Aware Scheduling in High-Level Synthesis,"  情報処理学会 組込み技術とネットワークに関するワークショップ （ETNET）, 2011-EMB-20(19), pp.1-6, 宮古島, 2011年7月.

  74. Takuya Azumi, Yuko Hara-Azumi, Shinya Honda, and Hiroaki Takada, "HW/SW Cosimulation Framework Based on Software Component System," 情報処理学会 組込み技術とネットワークに関するワークショップ （ETNET）, 2011-SLDM-149(44), 宮古島, 2011年7月.

  75. Yuko Hara-Azumi, Hiroyuki Tomiyama, and Hiroaki Takada, "Simultaneous Allocation and Binding Considering Multiplexers in High-Level Synthesis," 情報処理学会 SLDM研究会, 2011-SLDM-148(15), pp.1-6, 横浜市, 2011年1月. (※2011年度 情報処理学会山下記念研究賞受賞)

  76. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "関数レベル並列性を活用した動作記述分割手法," 情報処理学会 組込み技術とネットワークに関するワークショップ （ETNET）, pp.37-42, 屋久島, 2008年3月. (※第134回SLDM研究会優秀発表学生賞受賞)

  77. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "CHStone：Cベース高位合成のためのベンチマークスイート," 情報処理学会 DAシンポジウム, pp.157-162, 浜松市, 2007年8月.

  78. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "動作合成による倍精度浮動小数点型加算器の設計事例," 情報処理学会 EMB研究会, pp.1-6, 横浜市, 2007年1月.

  79. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, "動作合成におけるモジュール分割の最適化," 情報処理学会 DAシンポジウム , pp.607-612, 浜松市, 2006年7月.

Seminars

• 1. Yuko Hara-Azumi, "Power Side-channel Leakage and Its Countermeasure in the High Level Synthesis based Design Flow," Université libre de Bruxelles, Belgium, 2023年11月28日.

  2. Yuko Hara-Azumi, "Towards Lightweight and Secure Edge Computing," Technische Universiteit Delft, the Netherlands, 2023年11月24日.

  3. Yuko Hara-Azumi, "Integrating Side Channel Security into the High Level Synthesis based Design Flow," Chalmers University of Technology, Sweden, 2023年11月14日.

  4. Yuko Hara-Azumi, "Recent Trends in Lightweight and Secure Edge Computing," Technical University of Munich, Germany, 2023年10月30日.

  5. Yuko Hara-Azumi, "Power Side-channel Countermeasures for High-level Synthesis-designed Cipher Circuits," Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy, 2023年6月26日.

  6. Yuko Hara-Azumi, "Towards Power Side-channel Resistant Circuit Designs Using High-level Synthesis," Chair for Software for Systems on Silicon, RWTH Aachen University, Germany, 2023年6月21日.

  7. Yuko Hara-Azumi, "Side-channel Resistant Circuit Designs Using High-level Synthesis," COSIC Seminar, Katholieke Universiteit Leuven, Belgium, 2023年4月11日.

Press release

• 1. 東京工業大学/JST, "エッジ端末に適した小型省電力プロセッサを実証 従来比3.8倍のエネルギー効率でヘルスケアIoTに道," 2021年2月19日.

Media

• 1. 組込みシステム技術協会機関誌 Bulletin JASA, "IoTの可能性を広げるわずか1mm角の省電力プロセッサを設計 その成果と今後の展開 ～原祐子准教授に聞く", vol.83 (2022 Oct). 

  2. Top Researchers, "組み込みシステムの考え方に立ち返った、超小型・省力化CPUを開発し、次世代IoTのニーズに応える〜原 祐子・東京工業大学 工学院 准教授," 2022年7月19日.

  3. 日経産業新聞, "省電力のIoTプロセッサー," 2021年3月16日.

  4. 科学新聞, "IoT高度化に必要不可欠 小型省電力プロセッサ実現 エネルギー効率3.8倍 東工大がLSI開発," 2021年3月12日.

  5. JST Science Portal, "Society5.0の実現を支えるIoTとは？≪原祐子さんインタビュー≫＜令和3年版科学技術・イノベーション白書 特集＞," 2021年8月5日.

Others

• 1. 原 祐子, "Ｃ言語ベースハードウェア設計技法 (in Japanese)," 映像情報メディア学会 学会誌, vol.69, no.5, pp.422-444, 2015年5月.

  2. 安積 祐子, "High-Level Synthesis of LSIs from Large Behavioral Descriptions (in Japanese)," 情報処理 (特集 研究会推薦博士論文速報), vol.52 no.10, pp.1301, Oct. 2011.

  3. Yuko Hara, "High-Level Synthesis of LSIs from Large Behavioral Descriptions (in English)," Ph.D. dissertation, Nagoya University, Mar. 25, 2010.