Publications

Journals
  1. Takahiro Yamamoto, Ittetsu Taniguchi, Shigeru Yamashita, Hiroyuki Tomiyama, and Yuko Hara-Azumi, "A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers," IEICE Transactions on Fundamentals of Electronics, vol.E100-A, no.7, pp.1496-1499, Jul. 2017.
  2. Noriaki Sakamoto, Tanvir Ahmed, Jason Anderson, and Yuko Hara-Azumi, "SubleqΘ: An Area-Efficient Two-Instruction-Set Computer," IEEE Embedded Systems Letters, vol.9, Issue 2, pp. 33-36, Jun. 2017.
  3. Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Transactions on Information and Systems, vol.E97-D, no.11, pp.2827-2834, Nov. 2014.
  4. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs," IPSJ Transactions on System LSI Design Methodology, vol.7, pp.37-45, Feb. 2014. [Publication Site]
  5. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, and Yuko Hara-Azumi, "Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips," IEICE Transactions on Fundamentals of Electronics (Special Section on "VLSI Design and CAD Algorithms"), vol.E96-A, no.12, pp.2668-2679, Dec. 2013.
  6. Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Koji Inoue, "Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Transactions on Information and Systems, vol.E96-D, no.10, pp.2268-2271, Oct. 2013.
  7. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks," IPSJ Transactions on System LSI Design Methodology, vol.6, pp.122-126, Aug. 2013. [Publication Site]
  8. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Selective Check of Data-Path for Effective Fault Tolerance," IEICE Transactions on Information and Systems (Special Section on "Reconfigurable Systems"), vol.E96-D, no.8, pp.1592-1601, Aug. 2013.
  9. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism," IEICE Transactions on Fundamentals, vol.E93-A, no.2, pp.488-499, Feb. 2010.
  10. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis," Journal of Information Processing, vol.17, pp.242-254, Oct. 2009.  [Publication Site] (※平成21年度 情報処理学会東海支部学生論文奨励賞)
  11. Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, and Hiroaki Takada, "Embedded System Covalidation with RTOS Model and FPGA," IPSJ Transactions on System LSI Design Methodology, vol.1, pp.126-130, Aug. 2008. [Publication Site]
  12. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis," IEICE Transactions on Fundamentals, vol.E90-A, no.12, pp.2853-2862, Dec. 2007.
  13. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Function Call Optimization for Efficient Behavioral Synthesis," IEICE Transactions on Fundamentals, vol.E90-A, no.9, pp.2032-2036, Sep. 2007.
Papers @ International Conferences (Peer-reviewed)
  1. Hisashi Osawa and Yuko Hara-Azumi, "Approximate Data Reuse-based Processor: A Case Study on Image Compression," 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Seoul, Korea, Oct. 19th, 2017. (※accepted)
  2. Minato Yokota, Kaoru Saso, and Yuko Hara-Azumi, "One-Instruction Set Computer-based Multicore Processors for Energy-Efficient Streaming Data Processing," International Symposium on Rapid System Prototyping (RSP), Seoul, Korea, Oct. 19th, 2017. (※accepted)
  3. Goragod Pongthanisorn, Natavut Kwankeo, Kamol Kaemarungsi, and Yuko Hara-Azumi, "A Software Level Energy Efficient Algorithm on Real-Time Embedded System based on FreeRTOS," International Conference on Embedded Systems and Intelligent Technology (ICESIT2017), Bangkok, Thailand, Aug. 3rd, 2017
  4. Takahiro Yamamoto, Ittetsu Taniguchi, Shigeru Yamashita, Hiroyuki Tomiyama, and Yuko Hara-Azumi, "A Systematic Methodology for Design and Analysis of Approximate Array Multipliers,"Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 352-354, Jeju, Korea, Oct. 27th, 2016.
  5. Jason Anderson, Yuko Hara-Azumi, and Shigeru Yamashita, "Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy," Design, Automation & Test in Europe (DATE), pp. 1550-1555, Dresden, Germany, Mar. 17th, 2016.
  6. Tanvir Ahmed, Noriaki Sakamoto, Jason Anderson, and Yuko Hara-Azumi, "Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC," International Conference on Embedded and Ubiquitous Computing (EUC), pp. 114-123, Porto, Portugal, Oct. 22nd, 2015.
  7. Tanvir Ahmed and Yuko Hara-Azumi, "Timing Speculation-Aware Instruction Set Extension for Resource-Constrained Embedded Systems," Application-specific Systems, Architectures and Processors (ASAP), Toronto, Canada, pp.30-34, Jul. 27th, 2015.
  8. Takumi Tsuzuki, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.199-204, Yilan, Taiwan, Mar. 16th, 2015.
  9. Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, and Jason Anderson, "Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis," Design, Automation & Test in Europe (DATE), pp. 31-36, Grenoble, France, Mar. 10th, 2015.
  10. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Better-than-DMR Techniques for Yield Improvement," IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), p.34, Boston, MA, USA, May 12th, 2014.
  11. Yuko Hara-Azumi, Masaya Kunimoto, and Yasuhiko Nakashima, "Emulator-Oriented Tiny Processors for Unreliable Post-Silicon Devices: A Case Study," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.85-90, Singapore, Jan. 21nd, 2014.
  12. Takuya Azumi, Yasaman Samei Syahkal, Yuko Hara-Azumi, Hiroshi Oyama, and Rainer Dömer, "TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component," International Embedded Systems Symposium (IESS), pp.1-13, Paderborn, Germany, Jun. 17th, 2013.
  13. Ryoya Sobue, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Partial Controller Retiming in High-Level Synthesis," Electronic System Level Synthesis Conference (ESLsyn), pp.10-15, Austin, TX, USA, May 31nd, 2013.
  14. Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, and Mehdi Tahoori, "Instruction-Set Extension under Process Variation and Aging Effects," Design, Automation & Test in Europe (DATE), pp.182-187, Grenoble, France, Mar. 19th, 2013.
  15. Yuko Hara-Azumi and Hiroyuki Tomiyama, "Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation," International Symposium on Quality Electronic Design (ISQED), pp.518-523, Santa Clara, CA, USA, Mar. 5th, 2013.
  16. Yuko Hara-Azumi, Takuya Azumi, and Nikil D. Dutt, "VISA Synthesis: Variation-Aware Instruction Set Architecture Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.243-248, Yokohama, Japan, Jan. 23rd, 2013.
  17. Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, and Shigeru Yamashita, "A Redundant Wire Addition Method for Patchable Accelerator," International Conference on Electronics, Circuits, and Systems (ICECS), pp.552-555, Seville, Spain, Dec. 2012.
  18. Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, and Koji Inoue, "Task Mapping Techniques for Embedded Many-core SoCs," International SoC Design Conference (ISOCC), pp.204-207, Jeju, Korea, Nov. 2012.
  19. Yuko Hara-Azumi,  Toshinobu Matsuba,  Hiroyuki Tomiyama,  Shinya Honda,  and Hiroaki Takada, "Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis," International Conference on Embedded Software and Systems (ICESS), pp.1534-1540, Liverpool, UK, Jun. 26th, 2012.
  20. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, and Nikil D. Dutt, "High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.414-419, Oita, Japan, Mar. 9th, 2012.
  21. Daiki Tsuruta, Masayuki Wakizaka, Yuko Hara-Azumi, and Shigeru Yamashita, "A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.396-401, Oita, Japan, Mar. 2012.
  22. Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, and Shigeru Yamashita, "Bit Selective SAD and Its Evaluation," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.22-27, Oita, Japan, Mar. 2012.
  23. Yuko Hara-Azumi and Hiroyuki Tomiyama, "Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.251-256, Sydney, Australia, Feb. 2012.
  24. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.13-18, Taipei, Taiwan, Oct. 2010. 
  25. Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis," IEEE International Symposium on Electronic Design, Test & Applications (DELTA), pp.87-92, Ho Chi Minh City, Vietnam, Jan. 2010. 
  26. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Behavioral Partitioning with Exploiting Function-Level Parallelism," International SoC Design Conference (ISOCC), pp.121-124, Busan, Korea, Nov. 2008.
  27. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis," IEEE International Symposium on Circuits and Systems (ISCAS), pp.1192-1195, Seattle, WA, USA, May 2008.
  28. Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, and Hiroaki Takada, "Hardware/Software Covalidation with FPGA and RTOS Model," the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.488-494, Sapporo, Japan, Oct. 2007.
  29. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda , Hiroaki Takada, and Katsuya Ishii, "Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study," International Conference on Embedded Software and Systems (ICESS), pp.261-270, Daegu, Korea, May 2007.
  30. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii, "Complexity-Constrained Partitioning of Sequential Programs for Efficient Behavioral Synthesis," ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.365-370, Stresa, Italy, Mar. 2007.
  31. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "Function Call Optimization in Behavioral Synthesis," Euromicro Symposium on Digital System Design (DSD), pp.522-529, Cavtat, Croatia, Aug. 2006.
Invited talks @ International Conferences
  1. Yuko Hara-Azumi, "Energy-Efficient Multicore Processor for Large Stream Data in IoT Systems," 17th International Forum on MPSoC for Software-defined Hardware (MPSoC), Annecy, France, Jul. 4th, 2017.
  2. Yuko Hara-Azumi, Hisashi Osawa, and Tanvir Ahmed, "Architectural Approach on Approximate Computing for Media Processing," International Symposium on Nonlinear Theory and Its Applications (NOLTA), p.397, Yugawara, Nov. 29th, 2016.
  3. Yuko Hara-Azumi, "Area-Efficient Error Detection and Recovery for Dependable Embedded Systems," 16th International Forum on MPSoC for Software-defined Hardware (MPSoC), Nara, Japan, Jul. 14th, 2016.
  4. Yuko Hara-Azumi, Tanvir Ahmed, Takuya Azumi, and Nikil D. Dutt, "Instruction-Set Extension of Embedded Microprocessor for Timing Speculation," International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 67-72, Ho Chi Minh City, Vietnam, Aug. 11th, 2015.
  5. Yuko Hara-Azumi, "Partially-Programmable Circuit: New Flexible Method for Fault-Tolerance Improvement and Its Application," Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, Jun. 10th, 2015.
  6. Yuko Hara-Azumi, Toshihiko Kamata, Ittetsu Taniguchi, and Hiroyuki Tomiyama, "Yield-Aware Allocation and Binding of Partially-Programmable Functional Units," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp.729-732, Phuket, Thailand, Jul. 2nd, 2014.
  7. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, and Yuko Hara-Azumi, "A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidics Biochips," Asia and South Pacific Design Automation Conference (ASP-DAC), pp.199-204, Yokohama, Japan, Jan. 23rd, 2013.
  8. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Nikil Dutt, "Towards Practical High-Level Synthesis From Large Behavioral Descriptions," International SoC Design Conference (ISOCC), pp.71-74, Incheon, Korea, Nov. 2010.
Poster and Oral Presentations @ International Conferences/Symposia/Workshops 
  1. Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, and Yuko Hara-Azumi, "Systematic Design of Approximate Array Multipliers with Different Accuracy," International Workshop on Highly Efficient Neural Networks Design (HENND), Seoul, Korea, Oct. 20th, 2017. [Peer-reviewed, Poster Presentation] (※accepted)
  2. Kazuaki Hara and Yuko Hara-Azumi, "A Scalable FPGA Implementation of Amoeba-SAT Solver," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]
  3. Fransiscus Marcel Satria and Yuko Hara-Azumi, "Efficient Data Clustering by Architectural Perforation," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]
  4. Nguyen Hoang Ngoc Anh and Yuko Hara-Azumi, "Exploration of Hardware-Implementation-Aware Amoeba-SAT Solver," Multidisciplinary International Student Workshop (MISW), Tokyo, Aug. 9th, 2017. [Not peer-reviewed, Oral Presentation]
  5. Goragod Pongthanisorn, Natavut Kwankeo, Kamol Kaemarungsi, and Yuko Hara-Azumi, "Analysis of Energy Consumption Mode from Various Embedded System Application," International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES 2017), Chonburi Beach, Thailand, May 9th, 2017. [Peer-reviewed, Poster Presentation]
  6. Yuko Hara-Azumi, "Area-Efficient Error Recovery for Dependable Embedded Systems," EDA workshop in conjunction with ASP-DAC 2017 TPC Meeting, Hong Kong, Aug. 29th, 2016. [Not peer-reviewed, Oral Presentation]
  7. Kazuki Zenba, Tanvir Ahmed, and Yuko Hara-Azumi, "Fast and Simple Netlist-level Fault-Injection Framework on FPGA," IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIX, Yokohama, Apr. 21st-22nd, 2016. [Peer-reviewer, Poster Presentation]
  8. Noriaki Sakamoto, Tanvir Ahmed, Jason H. Anderson and Yuko Hara-Azumi, "Design Space Exploration of Flexible Heterogeneous Dual-Core Processor using MIPS and Extended OISC: A Case Study," 1st Workshop on Resource Awareness and Application Auto-tuning in Adaptive and Heterogeneous Computing (RES4ANT) in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 18th, 2016. [Peer-reviewed, Poster Presentation]
  9. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima, "Novel Area-Efficient Technique for Yield Improvement," Electronic System-Level Design towards Heterogeneous Computing in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 28th, 2014. [Not peer-Reviewed, Poster Presentation]
  10. Takuya Azumi, Yuko Hara-Azumi, and Rainer Dömer, "Virtual Platform Generation Using TECS Software Component and SCE," Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 16th, 2012. [Peer-reviewed, Poster Presentation]
  11. Takuya Azumi, Yuko Hara-Azumi, Shinya Honda, and Hiroaki Takada, "Software Component-Based HW/SW Cosimulation Framework: A Case Study," Work-In-Progress of Real-Time and Embedded Technology and Applications Symposium (RTAS), Chicago, IL, USA, Apr. 2011. [Peer-reviewed, Oral & Poster Presentation]
  12. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "The CHStone Benchmark Suite for Practical C-Based High-Level Synthesis," High-Level Synthesis: Next Step to Efficient ESL Design in conjunction with Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2009. [Not peer-reviewed, Oral Presentation]
  13. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada, "The CHStone Benchmark Suite for Practical C-Based High-Level Synthesis," High-Level Synthesis: Back to the Future in conjunction with Design Automation Conference (DAC), Anaheim, CA, USA, Jun. 2008. [Not peer-reviewed, Poster Presentation]
  14. Yuko Hara, "Efficient Behavioral Synthesis from Large Sequential Programs," Student Forum at Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, Jan. 2008. [Peer-reviewed, Poster Presentation]
Domestic Symposia (Peer-reviewed)
  1. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子,  "改良型配列型近似乗算器の設計と解析," 回路とシステムワークショップ, pp.13-18, 北九州, 2017年5月11日.
  2. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子, "配列型近似乗算器の設計と解析," 回路とシステムワークショップ, pp.237-242, 北九州, 2016年5月13日. 
  3. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, "動作合成における関数呼出しの最適化," 電子情報通信学会 第19回 回路とシステム軽井沢ワークショップ論文集, pp.607-612, 軽井沢, 2006年4月.
Domestic Symposia (Not peer-reviewed)
  1. 原 祐子, "高位合成の近年の研究動向 ~デバイス技術とアプリケーション多様化~," 回路とシステムワークショップ, p.19, 2017年5月11日. (※招待講演)
  2. 大澤 永始,Tanvir Ahmed,原 祐子,"Approximate Computingに基づいたデータ再利用型組込みプロセッサ," LSIとシステムのワークショップ,東京,2016年5月17日. [ポスター発表]
  3. 春日井 貴通,山下 茂,原 祐子,"Partially-Programmable Circuit を用いた遅延故障の回避手法," 情報処理学会 組込み技術とネットワークに関するワークショップ (ETNET), vol. 2016-EMB-40, no.25, pp.1-6, 五島, 2016年3月25日.
  4. 原 祐子, "国際会議採択に向けて ~留学・プログラム委員の経験から~," 情報処理学会 デザインガイア, p.69, 長崎, 2015年12月2日. (※招待講演)
  5. 酒本 典明, タンビア アーメド, ジェイソン アンダーソン, 原 祐子, "単一命令セットコンピュータの拡張とその評価," VLSI設計技術研究会 (VLD), pp. 19-24, 小樽, 2015年6月17日.
  6. 原 祐子, "システムレベル設計の研究動向," LSIとシステムのワークショップ 2015, 北九州, 2015年5月13日. (※招待講演)
  7. 杉山 翔一郎, タンビア アーメド, 原 祐子, "ルックアップテーブルを用いたapproximate computing向けアーキテクチャの実装と評価," VLSI設計技術研究会 (VLD), pp. 171-176, 那覇, 2015年3月4日.
  8. 谷口 一徹, 甲斐田 純也, 稗田 拓路, 原 祐子, 冨山 宏之,"数理計画アプローチによる動的タスク切り替えを考慮した組込みメニーコアSoC向けタスクマッピング," 計測自動制御学会 システム・情報部門 学術講演会 (SICE-SSI), p.1131, 岡山, 2014年11月. 
  9. 原 祐子, "組込みシステム上流設計の研究動向について(アーキテクチャとEDA)," 第90回STRJ-ERD会合, 2014年9月26日. (※招待講演)
  10. 都築 匠, 原 祐子, 山下 茂, 中島 康彦, "PPCにおけるLUT挿入位置最適化の定量的評価," 情報処理学会 DAシンポジウム, pp.67-72, 下呂, 2014年8月28日.
  11. 祖父江 亮哉, 原 祐子, 谷口 一徹, 冨山宏之, "高位合成におけるマルチプレクサの遅延の削減手法," 情報処理学会 組込み技術とネットワークに関するワークショップ (ETNET), 石垣島, 2014年3月15日.
  12. 祖父江 亮哉, 原 祐子, 谷口 一徹, 冨山宏之, "高位合成における制御回路の構成方法の定量的評価," 情報処理学会 デザインガイア, VLD2013-65, Vol. 113, No. 320, pp.257-262, 鹿児島, 2013年11月29日.
  13. 早苗 駿一, 原 祐子, 山下 茂, 中島 康彦, "PPCに基づく高歩留まり回路の発見的設計手法," 情報処理学会 デザインガイア, VLD2013-65, Vol. 113, No. 320, pp. 27-32, 鹿児島, 2013年11月27日. (※第163回SLDM研究会 優秀発表学生賞)
  14. 早苗 駿一, 原 祐子, 山下 茂, 中島 康彦, "Partially-Programmable Circuit の歩留まり向上のためのLUT 最適化手法," 情報処理学会 DAシンポジウム, pp. 27-32, 下呂, 2013年8月21日.
  15. 國本 将也, 原 祐子, 中島 康彦, "永久故障回避のための等価命令列置換手法," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, Vol.113, No.169, CPSY2013-30, pp.121-126, 北九州, 2013年7-8月. (※CPSY 優秀若手講演賞)
  16. 藤原 知広, 姚 駿, 原 祐子, 中島 康彦, "リング型アレイアクセラレータのマクロパイプライン化による性能見積もり," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.14, pp.1-6, 北九州, 2013年7-8月.
  17. 林 大地, 関 賀, 原 祐子, 姚 駿, 中島 康彦, "メモリ分散型アレイアクセラレータの浮動小数点演算に関する性能考察," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.8, pp.1-6, 北九州, 2013年7-8月.
  18. 稲垣 慶和, 原 祐子, 姚 駿, 中島 康彦, "リング型アレイアクセラレータ向け演算ライブラリの実装と性能評価," 情報処理学会 並列/分散/協調処理に関するサマー・ワークショップ SWoPP, 2013-ARC-206, No.1, pp.1-6, 北九州, 2013年7-8月.
  19. Hao Xu, Yuko Hara-Azumi, and Yasuhiko Nakashima, "Comparison of Emulation-Oriented 8-bit ISA with 6502 ISA for an ARM Emulator," 情報処理学会 ARC研究会, 2013-ARC-204 No.9, pp.1-6, 和歌山, 2013年3月.
  20. 祖父江 亮哉, 原 祐子, 稗田 拓路, 谷口 一徹, 冨山 宏之, "クロック周波数向上のための動作合成におけるコントローラ設計手法," 情報処理学会 デザインガイア, 2012-SLDM-158, No.20, pp.1-6, 福岡, 2012年11月27日. (※第158回SLDM研究会 優秀発表学生賞)
  21. Yuko Hara-Azumi,Takuya Azumi,and Nikil D. Dutt, "Instruction Set Architecture Synthesis Exploiting Process Variation," 情報処理学会 DAシンポジウム , pp.127-132, 下呂, 2012年8月.
  22. 甲斐田 純也,稗田 拓路,谷口 一徹,冨山 宏之,原 祐子,井上 弘士, "組込みメニーコア向けタスクマッピング手法," 情報処理学会 DAシンポジウム, pp.67-72, 下呂, 2012年8月.
  23. 鶴田 大貴,安積(原) 祐子,山下 茂, "リソースの再利用による実装面積を考慮した耐故障化高位合成手法," 情報処理学会 DAシンポジウム, pp.15-20, 下呂, 2011年8月.
  24. Yuko Hara-Azumi, Hiroyuki Tomiyama, Takuya Azumi, Shigeru Yamashita, Nikil D. Dutt, and Hiroaki Takada, "Soft Error-Aware Scheduling in High-Level Synthesis,"  情報処理学会 組込み技術とネットワークに関するワークショップ (ETNET), 2011-EMB-20(19), pp.1-6, 宮古島, 2011年7月.
  25. Takuya Azumi, Yuko Hara-Azumi, Shinya Honda, and Hiroaki Takada, "HW/SW Cosimulation Framework Based on Software Component System," 情報処理学会 組込み技術とネットワークに関するワークショップ (ETNET), 2011-SLDM-149(44), 宮古島, 2011年7月.
  26. Yuko Hara-Azumi, Hiroyuki Tomiyama, and Hiroaki Takada, "Simultaneous Allocation and Binding Considering Multiplexers in High-Level Synthesis," 情報処理学会 SLDM研究会, 2011-SLDM-148(15), pp.1-6, 横浜市, 2011年1月. (※2011年度 情報処理学会山下記念研究賞受賞)
  27. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "関数レベル並列性を活用した動作記述分割手法," 情報処理学会 組込み技術とネットワークに関するワークショップ (ETNET), pp.37-42, 屋久島, 2008年3月. (※第134回SLDM研究会優秀発表学生賞受賞)
  28. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "CHStone:Cベース高位合成のためのベンチマークスイート," 情報処理学会 DAシンポジウム, pp.157-162, 浜松市, 2007年8月.
  29. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, 石井 克哉, "動作合成による倍精度浮動小数点型加算器の設計事例," 情報処理学会 EMB研究会, pp.1-6, 横浜市, 2007年1月.
  30. 原 祐子, 冨山 宏之, 本田 晋也, 高田 広章, "動作合成におけるモジュール分割の最適化," 情報処理学会 DAシンポジウム , pp.607-612, 浜松市, 2006年7月.
Others
  1. 原 祐子, "C言語ベースハードウェア設計技法 (in Japanese)," 映像情報メディア学会 学会誌, vol.69, no.5, pp.422-444, 2015年5月.
  2. 安積 祐子, "High-Level Synthesis of LSIs from Large Behavioral Descriptions (in Japanese)," 情報処理 (特集 研究会推薦博士論文速報), vol.52 no.10, pp.1301, Oct. 2011.
  3. Yuko Hara, "High-Level Synthesis of LSIs from Large Behavioral Descriptions (in English)," Ph.D. dissertation, Nagoya University, Mar. 25, 2010.
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