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CHStone: The benchmark suite for C-based high-level synthesis
代表者,JST CREST "Trustworthy IoTシステム設計基盤の構築"(S5基盤)
代表者,JSPS 基盤(B) "近似計算型組込みシステムの効率的解析・設計のための基盤技術"
代表者,JSPS 二国間交流事業共同研究 (FWO) "組込みシステムセキュリティの保護と解析"
Apr. 2016 - present: Associate Professor at Hara Lab, Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology
Apr. 2023 - present: Research Area Adviser for JST ACT-X "Next AI-Math-Info"
Contact
(Main) Research Keywords
E-mail: hara_at_cad_dot_ict_dot_e_dot_titech_dot_ac_dot_jp
Mailing Address: S3-50, 2-12-1 Ookayama, Meguro 152-8552, Tokyo
Office: South Bldg. 3-317, Ookayama Campus
TEL/FAX: +81-3-5734-2914
Education
Apr. 2002 - Mar. 2006 : B.E. in Information Engineering, Nagoya University
Apr. 2006 - Mar. 2008 : M.E. in Graduate School of Information Science, Nagoya University
Apr. 2008 - Mar. 2010 : D.E. in Graduate School of Information Science, Nagoya University (Takada Lab)
Application-Specific Instruction set Processor (ASIP) - 特定用途向けプロセッサ
Computer Aided Design (CAD) - CAD
Cybersecurity - サイバーセキュリティ
Distributed computing - 分散コンピューティング
Domain-Specific Architecture (DSA) - ドメイン特化型アーキテクチャ
Edge computing - エッジコンピューティング
Electronic Design Automation (EDA) - 設計自動化
Embedded systems - 組込みシステム
Hardware security - ハードウェアセキュリティ
High-level synthesis - 高位合成
Instruction-set architecture (ISA) extension - 命令セットアーキテクチャ拡張
Internet-of-Things (IoT) - モノのインターネット
Machine learning - 機械学習
Cryptography with Advanced Functionality - 高機能暗号
Reconfigurable device/FPGA - 再構成可能デバイス/FPGA
System-level design - システムレベル設計
Job History
Research Interests
Sep. 2006 - Oct. 2006 : Research Intern at NEC System Technologies, Ltd.
Apr. 2008 - Mar. 2010 : Research fellow of the Japan Society for the Promotion of Science (DC1) at Takada Lab (ERTL), Nagoya University
Jul. 2010 - Dec. 2010 : Visiting scholar at Dutt Research Group, University of California, Irvine -> [CECS eNEWS]
Apr. 2010 - Mar. 2011: Visiting scholar at Tomiyama Lab (SLDM Lab), Ritsumeikan University
Apr. 2010 - Mar. 2011: Research fellow of the Japan Society for the Promotion of Science (PD) at Takada Lab (ERTL), Nagoya University
Sep. 2011 - Mar. 2012: Visiting scholar at Dutt Research Group, University of California, Irvine
Apr. 2012 - May 2012 : Visiting scientist at Chair for Embedded Systems (CES), Karlsruhe Institute of Technology, Germany -> [CES Events/News]
Apr. 2011 - May 2012 : Research fellow of the Japan Society for the Promotion of Science (PD) at Next Generation Computing (NGC Lab), Ritsumeikan University
Jun. 2012 - Dec. 2013: Assistant Professor at Computing Architecture Lab., Nara Institute of Science and Technology (NAIST)
Jan. 2014 - Mar. 2016: Associate Professor at Hara Lab, Department of Communications and Computer Engineering, Graduate School of Science and Engineering, Tokyo Institute of Technology (TITECH)
Apr. 2016 - present: Associate Professor at Hara Lab, Department of Information and Communications Engineering, Graduate School of Science and Engineering, Tokyo Institute of Technology (TITECH)
Apr. 2023 - Jul. 2023: Visiting Scholar at COSIC, Katholieke Universiteit Leuven, Belgium (Hosts: Dr. Svetla Nikova and Prof. Vincent Rijmen)
Feb. - Mar. 2024: Visiting Scholar at the Cybersecurity Research Center, Université libre de Bruxelles, Belgium (Host: Jan Tobias Mühlberg)
My research interests include, but not limited to:
System-level design methodology for IoT and embedded systems
High-level and logic synthesis
Benchmark suite for C-based high-level synthesis [CHStone website]
Instruction set architecture (ISA) synthesis
Hardware/software co-design
Approximate computing
FPGA designs
Hardware security
Cybersecurity
Hardware IP protection
Computer architecture
eHealth
Edge/distributed computing
Machine learning
Distributed machine learning
Intrusion detection
Neural Architecture Search (NAS)
Split computing
Society Membership
Links (about me)
Last update: Aug. 29, 2024