HOME


About Me
  • Last name:Hara (Married name:Azumi)  First name:Yuko
  • 姓:原 (安積) 名:祐子
  • Gender: Female
Position
Contact
  • E-mail: hara_at_cad_dot_ict_dot_e_dot_titech_dot_ac_dot_jp
  • Mailing Address: S3-50, 2-12-1 Ookayama, Meguro 152-8552, Tokyo
  • Office: South Bldg. 3-317, Ookayama Campus
  • TEL/FAX: +81-3-5734-2914
Education
  • Apr. 2002 - Mar. 2006 : B.E. in Information Engineering, Nagoya University
  • Apr. 2006 - Mar. 2008 : M.E. in Graduate School of Information Science, Nagoya University
  • Apr. 2008 - Mar. 2010 : D.E. in Graduate School of Information Science, Nagoya University (Takada Lab)
Employment History
Society Membership
  • ACM
  • IEEE Circuits and Systems Society (CASS)
  • IPSJ
  • IEICE
Ongoing Projects
(Main) Research Keywords
  • Embedded systems - 組込みシステム
  • High-level (or behavioral) synthesis - 高位合成(動作合成)
  • Logic synthesis - 論理合成
  • System-level design - システムレベル設計
  • Reconfigurable device/FPGA - 再構成可能デバイス/FPGA
  • Application-Specific Instruction set Processor (ASIP) - 特定用途向けプロセッサ
  • One Instruction Set Computer (OISC) -単一命令セットコンピュータ
  • Multi/Many-Core Processor - マルチ・メニーコアプロセッサ
  • Dependable/fault-tolerant systems - 耐故障システム
  • Compiler optimization - コンパイラ最適化
  • Approximate computing - 近似計算
  • Stochastic computing - 確率的計算
  • Computer Aided Design (CAD) - CAD
  • Electronic Design Automation (EDA) - 設計自動化
  • Post silicon device - ポストシリコンデバイス
  • Internet-of-Things (IoT) - モノのインターネット
  • Edge-Computing - エッジコンピューティング
  • Big Data - ビッグデータ
  • Deep Learning - 深層学習
  • Bio-inspired computing - 生物に学んだコンピューティング
  • Non von Neumann architecture - 非ノイマン型アーキテクチャ
  • Neural network - ニューラルネットワーク
  • SAT solver - SATソルバ
Research Interests
     
      My research interests include, but not limited to:
  • System-level design methodology for dependable/fault-tolerant systems and embedded systems
    • High-level and logic synthesis
    • Benchmark suite for C-based high-level synthesis [CHStone website]
    • Instruction set architecture (ISA) synthesis
    • Hardware/software co-design
    • Approximate/stochastic computing
    • FPGA designs
    • Bio-chip synthesis
    • Compiler optimizations
    • Fault detection and recovery
    • Solver for Satisfiability (SAT) problems
  • Architecture
    • Design and task mapping on multi/many-core processors
    • One Instruction-Set Computer (OISC)
  • Neural Network
    • Multi-modal neural networks
    • Hardware-oriented network optimization
    • Software optimization techniques for embedded systems
    • Distributed processing of neural networks by multiple microprocessors
    • Architectural designs based on memristive devices
    • Neuromorphic computing
Links