My publications on Google Scholar

Course Materials:

UC Berkeley EE230C for nanoelectronics https://www.overleaf.com/read/rxjrdbszpryb (overleaf account required)

Journal Papers:

1. Vita Pi-Ho Hu, Hung-Han Lin, Yen-Kai Lin, and Chenming Hu, "Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)," IEEE Trans. Electron Devices, vol. 67, no. 6, pp. 2593-2599, Jun. 2020. [Link]

2. Daewoong Kwon, Suraj Cheema, Yen-Kai Lin, Yu-Hung Liao, Korok Chatterjee, Ava J. Tan, Chenming Hu, and Sayeef Salahuddin, "Near Threshold Capacitance Matching in a NCFET with 1 nm EOT Gate Stack," IEEE Electron Device Lett., vol. 41, no. 1, pp. 179-182, Jan. 2020. [Link]

3. Yu-Hung Liao, Daewoong Kwon, Yen-Kai Lin, Chenming Hu, and Sayeef Salahuddin, "Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors," IEEE Electron Device Lett., vol. 40, no. 11, pp. 1860-1863, Nov. 2019. [Link]

4. Harshit Agarwal, C. Gupta, R. Goel, Pragya Kushwaha, Yen-Kai Lin, Min-Yen Kao, Juan Pablo Duarte, Huan-Lin Chang, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu, "BSIM-HV: High Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect," IEEE Trans. Electron Devices, vol. 66, no. 10, pp. 4258-4263, Oct. 2019. [Link]

5. Pragya Kushwaha, Harshit Agarwal, Yen-Kai Lin, Avirup Dasgupta, Ming-Yen Kao, Ye Lu, Yun Yue, Xiaonan Chen, Joseph Wang, Wing Sy, Frank Yang, PR Chidi Chidambaram, Sayeef Salahuddin, and Chenming Hu, "Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology node," IEEE Electron Device Lett., vol. 40, no. 6, pp. 985-988, Jun. 2019. [Link]

6. Yen-Kai Lin, Harshit Agarwal, Ming-Yen Kao, Jiuren Zhou, Yu-Hung Liao, Avirup Dasgupta, Pragya Kushwaha, Sayeef Salahuddin, and Chenming Hu, "Spacer Engineering in Negative Capacitance FinFETs," IEEE Electron Device Lett., vol. 40, no. 6, pp. 1009-1012, Jun. 2019. [Link]

7. Ming-Yen Kao, Yen-Kai Lin, Harshit Agarwal, Yu-Hung Liao, Pragya Kushwaha, Avirup Dasgupta, Sayeef Salahuddin, Chenming Hu, "Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly along the Channel," IEEE Electron Device Lett., vol. 40, no. 5, pp. 822-825, May 2019. [Link]

8. Yen-Kai Lin, Harshit Agarwal, Pragya Kushwaha, Ming-Yen Kao, Yu-Hung Liao, Korok Chatterjee, Sayeef Salahuddin, and Chenming Hu, "Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs," IEEE Trans. Electron Devices, vol. 66, no. 4, pp. 2023-2027, Apr. 2019. [Link]

9. Harshit Agarwal, Pragya Kushwaha, Yen-Kai Lin, Ming-Yen Kao, Yu-Hung Liao, Avirup Dasgupta, Sayeef Salahuddin, Chenming Hu, "Proposal for Capacitance Matching in Negative Capacitance Field Effect Transistors," IEEE Electron Device Lett., vol. 40, no. 3, pp. 463-466, Mar. 2019. [Link]

10. Ming-Yen Kao, Angada Sachid, Yen-Kai Lin, Yu-Hung Liao, Harshit Agarwal, Pragya Kushwaha, Juan Pablo Duarte, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, "Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor," IEEE Trans. Electron Devices, vol. 65, no. 10, pp. 4652-4658, Oct. 2018. [Link]

11. Harshit Agarwal, Pragya Kushwaha, Yen-Kai Lin, Ming-Yen Kao, Yu-Hung Liao, Juan-Pablo Duarte, Sayeef Salahuddin, and Chenming Hu, "NCFET Design Considering Maximum Interface Electric Field," IEEE Electron Device Lett., vol. 39, no. 8, pp. 1254-1257, Aug. 2018. [Link]

12. Pragya Kushwaha, Harshit Agarwal, Yen-Kai Lin, Ming-Yen Kao, Juan Pablo Duarte, Huan-Lin Chang, W. Wong, J. Fan, Yogesh S. Chauhan, Sayeef Salahuddin and Chenming Hu, "Modeling of advanced RF Bulk FinFETs," IEEE Electron Device Lett., vol. 39, no. 6, pp. 791-794, Jun. 2018. [Link]

13. Harshit Agarwal, Pragya Kushwaha, Juan Pablo Duarte, Yen-Kai Lin, Angada Sachid, Ming-Yen Kao, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, "Engineering Negative Differential Resistance in NCFETs for Analog Applications," IEEE Trans. Electron Devices, vol. 65, no. 5, pp. 2033–2039, May. 2018. [Link]

14. Harshit Agarwal, Pragya Kushwaha, Juan Pablo Duarte, Yen-Kai Lin, Angada Sachid, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, "Designing 0.5V 5nm HP and 0.23V 5nm LP NC-FinFETs with Improved Ioff Sensitivity in Presence of Parasitic Capacitance," IEEE Trans. Electron Devices, vol. 65, no. 3, pp. 1211–1216, Mar. 2018. [Link]

15. Yen-Kai Lin, Pragya Kushwaha, Juan Pablo Duarte, Huan-Lin Chang, Harshit Agarwal, Sourabh Khandelwal, Angada Sachid, Michael Harter, Josef Watts, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu, "New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs," IEEE Trans. Electron Devices, vol. 65, no. 2, pp. 463–469, Feb. 2018. [Link]

16. Yen-Kai Lin, Pragya Kushwaha, Harshit Agarwal, Huan-Lin Chang, Juan Pablo Duarte, Angada Sachid, Sourabh Khandelwal, Sayeef Salahuddin, and Chenming Hu, "Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTBSOI MOSFETs," IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 3986–3990, Oct. 2017. [Link]

17. Yen-Kai Lin, Juan Pablo Duarte, Pragya Kushwaha, Harshit Agarwal, Huan-Lin Chang, Angada Sachid, Sayeef Salahuddin, and Chenming Hu, "Compact Modeling Source-to-Drain Tunneling in Sub-10nm GAA FinFET with Industry Standard Model," IEEE Trans. Electron Devices, vol. 64, no. 9, pp. 3576–3581, Sep. 2017. [Link]

18. Chetan Gupta, Harshit Agarwal, Yen-Kai Lin, Akira Ito, Chenming Hu, and Yogesh Singh Chauhan, “Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model,” Jpn. J. Appl. Phys., vol. 56, no. 4S, pp. 04CD09-1–04CD09-6, Mar. 2017. [Link]

19. Yen-Kai Lin, Sourabh Khandelwal, Juan Pablo Duarte, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, “A Predictive Tunnel FET Compact Model with Atomistic Simulation Validation,” IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 599–605, Feb. 2017. [Link]

20. Yen-Kai Lin, Sourabh Khandelwal, Aditya Medury, Harshit Agarwal, Huan-Lin Chang, Yogesh Singh Chauhan, and Chenming Hu, “Modeling of Sub-surface Leakage Current in Low VTH Short Channel MOSFET at Accumulation Bias,” IEEE Trans. Electron Devices, vol. 63, no. 5, pp. 1840–1845, May 2016. [link]

21. Yen-Kai Lin, Huang-Hsuan Lin, and Jenn-Gwo Hwu, “Characterization of Ambient Light Induced Inversion Current in MOS(n) Tunneling Diode with Enhanced Oxide Thickness Dependent Performance,” IEEE Trans. Electron Devices, vol. 63, no. 1, pp. 384–389, Jan. 2016. [link]

22. Huang-Hsuan Lin, Yen-Kai Lin, and Jenn-Gwo Hwu, “Non-Uniform Hole Current Induced Negative Capacitance Phenomenon Examined By Photo-Illumination in MOS(n),” ECS Transactions, vol. 69, no. 5, pp. 261–265, Oct. 2015. [Link]

23. Yen-Kai Lin and Jenn-Gwo Hwu, “Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3562–3565, Oct. 2014. [Link]

24. Yen-Kai Lin and Jenn-Gwo Hwu, “Photosensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3217–3222, Sept. 2014. [Link]

25. Yen-Kai Lin, Li Lin, and Jenn-Gwo Hwu, “Minority Carriers Induced Schottky Barrier Height Modulation in Current Behavior of Metal-Oxide-Semiconductor Tunneling Diode,” ECS J. Solid State Sci. Technol., vol. 3, no. 6, pp. Q132–Q135, May 2014. [Link]

Conference Papers: 

1. L.-C. Wang, W. Li, N. Shanker, S. S. Cheema, S.-L. Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Y.-K. Lin, C. Hu, S. Salahuddin, "Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack," Symposia on VLSI Technology and Circuits, Kyoto, Japan, Jun. 2023. [Link]

2. Yen-Kai Lin, Jing Wang, Takeshi Okagaki, Seonghoon Jin, Anh-Tuan Pham, Yonghee Park, Uihui Kwon, Woosung Choi, and Dae Sin Kim, "Negative-Capacitance FETs for Advanced Nodes: Circuit Performance and Variability Analysis with Ferroelectric Dynamic Switching," International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Dallas, TX, USA, Sep. 2021. [Link]

3. Ramin Rajaei, Yen-Kai Lin, Sayeef Salahuddin, Michael Niemier, and Xiaobo Sharon Hu, "Dynamic memory and sequential logic design using negative capacitance finfets," IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, Otc. 2020. [Link]

4. Ramin Rajaei, Yen-Kai Lin, Sayeef Salahuddin, Michael Niemier, Xiaobo Sharon Hu, "GC-eDRAM design using hybrid FinFET/NC-FinFET," Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, Aug. 2020. [Link]

5. Pragya Kushwaha, Harshit Agarwal, Varun Mishra, Avirup Dasgupta, Yen-Kai Lin, Ming-Yen Kao, Yogesh Singh Chauhan, Sayeef Salahuddin, and Chenming Hu, "Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, California, USA, Oct. 2019. [Link]

6. Yen-Kai Lin, Ming-Yen Kao, Harshit Agarwal, Yu-Hung Liao, Pragya Kushwaha, Korok Chatterjee, Juan Pablo Duarte, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, "Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability," IEEE International Electron Devices Meeting (IEDM), San Francisco, California, USA, Dec. 2018. [Link]

7. Juan Pablo Duarte, Yen-Kai Lin, Yu-Hung Liao, Angada Sachid, Ming-Yen Kao, Harshit Agarwal, Pragya Kushwaha, Korok Chatterjee, Daewoong Kwon, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, "Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation," International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, TX, USA, Sep. 2018. [Link]

8. Daewoong Kwon, Yu-Hung Liao, Yen-Kai Lin, Juan Pablo Duarte, Korok Chatterjee, Ava J. Tan, Ajay K. Yadav, Chenming Hu, Zoran Krivokapic, and Sayeef Salahuddin, "Response Speed of Negative Capacitance FinFETs," Symposia on VLSI Technology and Circuits, Honolulu, HI, USA, Jun. 2018. [Link]

9. Pragya Kushwaha, Harshit Agarwal, Chetan Dabhi, Yen-Kai Lin, Juan Pablo Duarte, Chenming Hu, and Yogesh S. Chauhan, "A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect," IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, 2018.

10. Pragya Kushwaha, Juan Pablo Duarte, Yen-Kai Lin, Harshit Agarwal, Huan-Lin Chang, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu, "Unified Compact Model for Gate All Around FETs-Nanosheets, Nanowires, Multi Bridge Channel MOSFETs," 2018 Workshop on Compact Modeling (WCM), Anaheim, CA, USA, May 2018.

11. Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Tamilmani Ethirajan, Chenming Hu, and Yogesh S. Chauhan, "Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs," 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, India, Jan. 2017. [Link]

12. Juan Pablo Duarte, Sourabh Khandelwal, Asif I. Khan, Angada B. Sachid, Yen-Kai Lin, Huan-Lin Chang, Sayeef Salahuddin, and Chenming Hu, “Compact Models of Negative-Capacitance FinFETs: Lumped and Distributed Charge Models,” IEEE International Electron Devices Meeting (IEDM), San Francisco, California, USA, Dec. 2016. [Link]

13. Chetan Gupta, Harshit Agarwal, Yen-Kai Lin, Sourabh Khandelwal, Akira Ito, Chenming Hu, Yogesh Singh Chauhan, “Analysis and Modeling of Zero-VTH Native Devices with Industry Standard BSIM6 Model,” International Conference on Solid State Devices and Materials (SSDM2016), Tsukuba, Japan, Sep. 2016.

14. Chetan Gupta, Harshit Agarwal, Yogesh Singh Chauhan, Sourabh Khandelwal, Yen-Kai Lin, Chenming Hu, and Renaud Gillon, “Modeling of High Voltage LDMOSFET using Industry Standard BSIM6 MOS Model,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Aug. 2016. [Link]

15. Pragya Kushwaha, Harshit Agarwal, Yogesh Singh Chuahan, Mandar Bhoir, Nihar R. Mohapatra, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, and Chenming Hu, “Predictive Effective Mobility Model for FDSOI Transistors using Technology Parameters,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Aug. 2016. [Link]

16. Pragya Kushwaha, Rahul Agarwal, Harshit Agarwal, Chetan Gupta, Yogesh Singh Chuahan, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, and Chenming Hu, “Modeling of Threshold Voltage for Operating Point using Industry standard BSIM-IMG Model,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Aug. 2016. [Link]

17. Harshit Agarwal, Pragya Kushwaha, Yogesh Singh Chuahan, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, Chenming Hu, Heng Wu, and Peide D. Ye, “Modeling of GeOI and Experimental Validation with Ge-CMOS Circuit using BSIM-IMG Industry Standard Model,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Aug. 2016. [Link]

18. Juan Pablo Duarte, Sourabh Khandelwal, Huan-Lin Chang, Yen-Kai Lin, Pragya Kushwaha, Yogesh Singh Chauhan, and Chenming Hu, “Modeling Independent Multi-Gate MOSFET,” 2016 Workshop on Compact Modeling (WCM), Washington DC, USA, May 2016.

19. Huang-Hsuan Lin, Yen-Kai Lin, and Jenn-Gwo Hwu, “Non-Uniform Hole Current Induced Negative Capacitance Phenomenon Examined By Photo-Illumination in MOS(n),” 228th ECS Meeting, Phoenix, Arizona, USA, Oct. 2015. [Link]

20. Po-Hao Tseng, Yen-Kai Lin, Han-Wei Lu, Yu-Ching Liao, and Jenn-Gwo Hwu, “Nanoscale Oxide Engineering on Si Substrate,” International Electronic Devices and Materials Symposium IEDMS 2014, Hualien, Taiwan, Nov. 2014.

21. Yen-Kai Lin and Jenn-Gwo Hwu, “Role of Lateral Diffusion Current in Gate Current Characteristics of MOS(p) and MOS(n) Capacitors with Ultrathin (< 3 nm) Oxides,” Nano Science & Technology – Nano S&T 2014, Qingdao, China, Oct. 2014.