Journal Papers (Total: 75)

J75. Yunbo Huang, Yong Chen*, Pui-In Mak, and Rui P. Martins, “Universal Stability Criterion for Type-I Sampling Phase-Locked Loops,” IEEE Transactions on Circuits and Systems - II, vol. xx, no. xx, pp. xxxx-xxxx, Mar. 2023.

J74. Yunbo Huang, Yong Chen*, Bo Zhao, Pui-In Mak, and Rui P. Martins, “A 3.6-GHz Type-II Sampling PLL with a Differential Parallel-Series Double-Edge S-PD Scoring 43-fsRMS Jitter, -258.7-dB FOM and -79.19-dBc Reference Spur,” IEEE Transactions on Very Large Scale Integration Systems, vol. 31, no. 2, pp. 188-198, Feb. 2023.

J73. Yunbo Huang, Yong Chen*, Bo Zhao, Pui-In Mak, and Rui P. Martins, “A 3.78-GHz Type-I Sampling PLL with a Fully-Passive KPD-Doubled Master-Slave S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM and -70.96-dBc Reference Spur,” IEEE Transactions on Circuits and Systems - I, vol. 70, no. 4, pp. 1463-1475, Apr. 2023.

J72. Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, and Shunli Ma, “A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. xx, no. xx, pp. xxxx-xxxx, Mar. 2023.

J71. Lin Wang,  Yong Chen*,  Chaowei Yang,  Xionghui Zhou,  Mei Han,  Crovetti Paolo Stefano,  Pui-In Mak,  Rui P. Martins, “A 6-to-38 Gb/s Capture-Range Bang-Bang Clock and Data Recovery Circuit with Deliberate-Current-Mismatch Frequency Detection and Interpolation-Based Multi-Phase Clock Generation,” International Journal of Circuit Theory and Applications, vol. xx, no. xx, pp. xxxx-xxxx, Nov. 2022.

J70. Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Yong Chen, Pui-In Mak, and Rui P. Martins, “High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review,” IEEE Access, vol. 11, pp. 11143-11164, 2023. 

J69. Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Yong Chen, Pui-In Mak, and Rui P. Martins, “Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview,” IEEE Access, vol. 10, pp. 126910-126930, 2022. 

J68. Wen Xun Lian, Jack Kee Yong, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Yong Chen, Pui-In Mak, and Rui P. Martins, “A Reconfigurable Hybrid RF-front-end Rectifier for Dynamic-PCE/Sensitivity Enhancement of Ambient RF Energy Harvesting System,” Electronics, vol. 12, no. 1, p. 175, Dec. 2022. 

J67. Qirui Ren, Chengying Chen, Danian Dong, Xiaoxin Xu, Yong Chen, and Feng Zhang, “A 13-μW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection,” Sensors, vol. 22, no. 16, p. 6096, Aug. 2022. 

J66. Qirui Ren, Qiang Huo, Zhisheng Chen, Feihong Chen, Qi Gao, Yiming Wang, Yiming Yang, Tian Wang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei*, Xinghua Wang*, Feng Zhang*, Yong Chen*, and Pui-In Mak, “A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF,” IEEE Transactions on Very Large Scale Integration Systems, vol. 31, no. 2, pp. 243-252, Feb. 2023. 

J65. Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, and Shunli Ma, “A 4.5-W, 18.5–24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique,” IEEE Transactions on Very Large Scale Integration Systems, vol. 31, no. 2, pp. 233-242, Feb. 2023. 

J64. Tan Yee Chyan, Harikrishnan Ramiah, S. F. Wan Muhamad Hatta, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, and Rui P. Martins, “Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review,” IEEE Access, vol. 10, pp. 114469-114489, 2022. 

J63. Ziyi Chang, Yunshan Zhang, Changgui Yang, Yuxuan Luo, Yong Chen, and Bo Zhao, “A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems,” IEEE Transactions on Circuits and Systems - I, vol. 69, no. 12, pp. 4981-4992, Dec. 2022. 

J62. Xi Wang,  Dong Wei,  Zhiyang Zhang,  Tianxiang Wu,  Xu Chen,  Yong Chen,  Junyan Ren,  Shunli Ma, “A 90-115GHz Superheterodyne Receiver Front-End for W-band Imaging System in 28-nm CMOS,” International Journal of Circuit Theory and Applications, vol. 51, no. 4, pp. 1530-1547, Nov. 2022.

J61. Tianhui Yuan, Jianyu Fu, Yong Chen, Yihong Lu, Ying Hou, Guanjun Sun, and Dapeng Chen, “Pulse-Voltage-Based Thermal Parameters Extraction Method for Thermopile Infrared Sensors,” IEEE Sensors Journal, vol. 23, no. 6, pp. 5593-5600, Mar. 2023. 

J60. Yong Chen*, and Harikrishnan Ramiah, “APCCAS 2021 Guest Editorial,” IEEE Transactions on Circuits and Systems - I, vol. 69, no. 11, pp. 4331-4331, Nov. 2022. [Invited]

J59. Zhuofan Xu, Biao Hu, Tianxiang Wu, Yuting Yao, Yong Chen, Junyan Ren, and Shunli Ma, “A 12-bit 50-MS/s Split-CDAC-based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer,” Electronics, vol. 11, no. 12, p. 1841, Jun. 2022. 

J58. Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, and Shunli Ma, “A 6.5-mm2 10.5-to-15.5GHz Differential GaN PA with Coupled-Line-Based Matching Networks Achieving 10-W Peak Psat and 42% PAE,” IEEE Transactions on Circuits and Systems - II, vol. 69, no. 11, pp. 4268-4272, Nov. 2022. 

J57. Xiangdong Feng, Yunshan Zhang, Yangfan Xuan, Zhuhao Li, Changgui Yang, Xin Xie, Yuxuan Luo, Xiangwei Zhao, Yong Chen, and Bo Zhao, “A Square-Wave Stimulated DNA Analyzer Chip Featuring 120µW Power Consumption and Simultaneous Dual-Frequency Detection,” IEEE Transactions on Circuits and Systems - II, vol. 69, no. 10, pp. 4093-4097, Oct. 2022. 

J56. Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Yong Chen, Pui-In Mak, and Rui P. Martins, “A −20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN,” IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 11, pp. 1808-1812, Nov. 2022. 

J55. Alexander Choo, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Saad Mekhilef, Yong Chen, Pui-In Mak, and Rui P. Martins, “A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting,” IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 10, pp. 1533-1537, Oct. 2022. 

J54. Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Gabriel Chong, Yong Chen, Pui-In Mak, and Rui P. Martins, “A Fully-Integrated Ambient RF Energy-Harvesting System with 423-μW Power,” Sensors, vol. 22, no. 12, p. 4415, Jun. 2022. 

J53. Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.1-VIN Subthreshold 3-Stage Cross-Coupled Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias,” IEEE Transactions on Circuits and Systems - II, vol. 69, no. 9, pp. 3929-3933, Sep. 2022. 

J52. Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, and Nan Qi, “Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects,” IEEE Transactions on Circuits and Systems - I, vol. 69, no. 11, pp. 4345-4357, Nov. 2022. [Invited]

J51. Yong Chen*, Pui-In Mak, and Rui P. Martins, “High-Performance Harmonic-Rich Single-Core VCO with Multi-LC Tank: A Tutorial,” IEEE Transactions on Circuits and Systems - II, vol. 69, no. 7, pp. 3115-3121, Jul. 2022. [Invited]

J50. Xiaoteng Zhao, Yong Chen*, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, “A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1358-1371, May 2022. [Invited]

J49. Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, and Shunli Ma, “A 23-to-28 GHz 5-bit Switch-Type Phase Shifter With 1-bit Calibration Based on Optimized ABCD Matrix Design Methods for 5G MIMO System in 0.15-μm GaAs,” International Journal of Circuit Theory and Applications, vol. 50, no. 6, pp. 1834-1854, Jun. 2022.

J48. Qihui Zhang, Ning Ning, Zhong Zhang, Jing Li, Kejun Wu, Yong Chen, and Qi Yu, “A 13-bit ENOB Third-Order PVT-Insensitive Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration,” IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2181-2195, Jul. 2022.

J47. Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leiliang Li, Guike Li, Zhao Zhang,  Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, and Nan Qi, “A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, CMOS Distributed Driver, and Integrated CDR,” IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 767-780, Mar. 2022. [Invited]

J46. Rui P. Martins, Pui-In Mak, Sai-Weng Sin, Man-Kay Law, Yan Zhu, Yan Lu, Jun Yin, Chi-Hang Chan, Yong Chen, Ka-Fai Un, Mo Huang, Minglei Zhang, Yang Jiang, and Wei-Han Yu, “Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques Towards the Future Internet of Everything (IoE) Applications,” Foundations and Trends in Integrated Circuits and Systems, vol. 1, no. 2-3, pp. 72-216, Nov. 2021. [Invited]

J45. Zunsong Yang, Yong Chen*, Jia Yuan, Pui-In Mak, and Rui P. Martins, "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM,” IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 2, pp. 238-242, Feb. 2022. 

J44. Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, and Nan Qi, “A 56-Gb/s Configurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS,” IEEE Transactions on Circuits and Systems - I, vol. 69, no. 3, pp. 1159-1170, Mar. 2022. 

J43. Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, and Shunli Ma, “A 10MHz-to-50GHz Low-Jitter Multi-Phase Clock Generator for High-Speed Oscilloscope in 0.15-µm GaAs Technology,” International Journal of Circuit Theory and Applications, vol. 50, no. 2, pp. 367-381, Apr. 2022.

J42. Xiaoteng Zhao, Yong Chen*, Pui-In Mak, and Rui P. Martins, “A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2(Gb/s)/µs Acquisition Speed of the PAM-4 Input in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 546-561, Feb. 2022.  

J41. Yiqing Mao, Tianxiang Wu, Yong Chen, Junyan Ren, and Shunli Ma, “A 0.2-Terahertz Ceramic Relic Detection System Based on Iterative Threshold Filtering Imaging and Neural Network,” Electronics, vol. 10, no. 18, p. 2213, Sep. 2021. [Cover Story]  

J40. Siyuan Yang, Songyi Li, Jiayan Wu, Yong Chen, and Zhenyu Liu, “An FPGA-Based Accelerated Architecture of Change-Point Detection for FMCW Radar Interference,” International Journal of Circuit Theory and Applications, vol. 49, no. 11, pp. 3719-3732, Nov. 2021.

J39. Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Jin Wu, Lei Zhou, and Xinyu Liu, “A 1.55-to-32-Gb/s Four-Lane Fully-Integrated Transmitter with 3-Tap Feed Forward Equalizer in 28nm CMOS,” Electronics, vol. 10, no. 16, p. 1873, Aug. 2021.

J38. Tianxiang Wu, Jipeng Wei, Hongquan Liu, Shunli Ma, Yong Chen, and Junyan Ren, “A Sub-6GHz SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Communication in 0.25-μm GaAs Technology,” Electronics, vol. 10, no. 12, p. 1482, Jun. 2021.

J37. Hao Guo, Yong Chen*, Chaowei Yang, Pui-In Mak, and Rui P. Martins, “A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RCLM Tank,” IEEE Transactions on Circuits and Systems - I, vol. 69, no. 1, pp. 172-185, Jan. 2022. [ISICAS’2021] 

J36. Yunbo Huang, Yong Chen*, Hailong Jiao, Pui-In Mak, and Rui P. Martins, “A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques,” IEEE Transactions on Circuits and Systems - II, vol. 68, no. 9, pp. 3093-3097, Sep. 2021. [ISICAS’2021]

J35. Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, and Junyan Ren, “A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65nm CMOS,” IEEE Access, vol. 9, pp. 77545-77554, May 2021.

J34. Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, and Junyan Ren, “A 120-150GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System,” IEEE Access, vol. 9, pp. 74752-74762, May 2021. 

J33. Selvakumar Mariappan, Jagadheswaran Rajendran, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 1.7-to-2.7GHz 35-38% PAE Reconfigurable Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Predistorter (DAAPD) Linearization Technique,” IEEE Transactions on Circuits and Systems - II, vol. 68, no. 11, pp. 3381-3385, Nov. 2021.

J32. Fangzhou Sun, Yushi Zhou, Zhanjun Bai, and Yong Chen, “A 190.3-dBc/Hz FoM 16-GHz Rotary Travelling-Wave Oscillator With Reliable Direction Control,” IET Electronics Letters, vol. 57, no. 5, pp. 209-211, Mar. 2021.

J31. Lingshan Kong, Yong Chen*, Haohong Yu, Chirn Chye Boon, Pui-In Mak, and Rui P. Martins, "Wideband Variable-Gain Amplifiers Based on a Pseudo-Current Steering Gain-Tuning Technique,” IEEE Access, vol. 9, pp. 35814-35823, Feb. 2021.

J30. Zunsong Yang, Yong Chen*, Pui-In Mak, and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS,” IEEE Transactions on Circuits and Systems - I, vol. 68, no. 6, pp. 2307-2316, Jun. 2021. 

J29. Rui P. Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, and Sai-Weng Sin, “Bird's-eye view of Analog and Mixed-Signal Chips for the 21st Century,” International Journal of Circuit Theory and Applications, 2021; 49: 746–761. https://doi. org/10.1002/cta.2958. [Invited]

J28. Xiaoteng Zhao, Yong Chen*, Pui-In Mak, and Rui P. Martins, “A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS,” IEEE Transactions on Circuits and Systems - I, vol. 65, no. 9, pp. 3014-3026, Jan. 2021. [Invited]

J27. Zunsong Yang, Yong Chen*, Pui-In Mak, and Rui P. Martins, "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM,” IEEE Solid-State Circuits Letters, vol. 3, pp. 494-497, 2020. 

J26. Yunbo Huang, Yong Chen*, Hao Guo, Pui-In Mak, and Rui P. Martins, “A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays with a 187.6-dBc/Hz FOM,” IEEE Transactions on Circuits and Systems - I, vol. 67, no. 11, pp. 3704-3711, Nov. 2020. [ISICAS’2020]

J25. Haohong Yu, Yong Chen*, Chirn Chye Boon, Pui-In Mak, and Rui P. Martins, “A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration,” IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 1, pp. 144-159, Jan. 2020.

J24. Zunsong Yang, Yong Chen*, Shiheng Yang, Pui-In Mak, and Rui P. Martins, “A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector," IEEE Access, vol. 8, pp. 2222-2232, Dec. 2019.

J23. Yong Chen*, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, and Rui P. Martins, “A 0.0071-mm2 10.8pspp-Jitter 4-to-10Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis,” IEEE Transactions on Circuits and Systems - I, vol. 66, no. 10, pp. 3991-4004, Oct. 2019.

J22. Xiaoteng Zhao, Yong Chen*, Pui-In Mak, and Rui P. Martins, “A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using Auxiliary Negative-gm Cell,” IEEE Transactions on Circuits and Systems - I, vol. 65, no. 9, pp. 3014-3026, May 2019. [ISICAS’2019]

J21. Xinyi Ge, Yong Chen*, Xiaoteng Zhao, Pui-In Mak, and Rui P. Martins, “Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With Second-Order Loop Filter,” IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 3, pp. 599-603, Nov. 2019.

J20. Yong Chen*, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, Pui-In Mak, and Rui P. Martins, “A 6.5x7µm2 0.98-to-1.5mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44GHz),” IEEE Solid-State Circuits Letters, vol. 1, no. 4, pp. 86-89, Apr. 2019.

J19. Hao Guo, Yong Chen*, Pui-In Mak, and Rui P. Martins, "A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO with a 189.6-dBc/Hz FOM,” IEEE Solid-State Circuits Letters, vol. 1, no. 4, pp. 86-89, Apr. 2018. 

J18. Haohong Yu, Yong Chen*, Chirn Chye Boon, Chenyang Li, Pui-In Mak, and Rui P. Martins, "A 0.44-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB,” IEEE Transactions on Circuits and Systems - II, vol. 66, no. 10, pp. 71-75, Jan. 2019.

J17. Yong Chen*, Pui-In Mak, Chirn Chye Boon, and Rui P. Martins, “A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin,” IEEE Transactions on Circuits and Systems - I, vol. 65, no. 9, pp. 3014-3026, Sep. 2018. 

J16. Lingshan Kong, Yong Chen*, Chirn Chye Boon, Pui-In Mak, and Rui P. Martins, “A Wideband Inductorless dB-Linear Automatic-Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications,” IEEE Transactions on Circuits and Systems - I, vol. 65, no. 10, pp. 3196-3206, Oct. 2018. 

J15. Sharma Sunny, Yong Chen, and Chirn Chye Boon, “A 4.06-mW 10-bit 150-MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications,” IEEE Sensors Journal, vol. 18, no. 11, pp. 4553-4560, Jun. 2018. 

J14. Arya Balachandran, Yong Chen, and Chirn Chye Boon, “A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Loss in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 3, pp. 599-603, Mar. 2018. 

J13. Arya Balachandran, Yong Chen, and Chirn Chye Boon, “A 0.058mm2 13Gb/s Inductorless Analogue Equaliser with Low-Frequency Equalisation Compensating 15 dB Channel Loss,” IET Electronics Letters, vol. 54, no. 2, pp. 72-74, Jan. 2018. 

J12. Yong Chen*, Pui-In Mak, Haohong Yu, Chirn Chye Boon, and Rui P. Martins, “An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling,” IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 12, pp. 4960-4975, Dec. 2017. 

J11. Yong Chen*, Pui-In Mak, Chirn Chye Boon, and Rui P. Martins, “A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS,” IEEE Microwave Wireless Components Letters, vol. 27, no. 9, pp. 839-841, Sep. 2017.

J10. Yong Chen, Pui-In Mak, and Yan Wang, "A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links," IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 5, pp. 978-982, May 2015.   

J9. Yong Chen, Pui-In Mak, Li Zhang, and Yan Wang, "A 0.002-mm2 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver with 59.6% Horizontal Eye Opening at 10-12 BER Under 23.3-dB Channel Loss at Nyquist," IEEE Transactions on Microwave Theory and Techniques,  vol. 62, no. 12, pp. 3107-3117, Dec. 2014. 

J8. Yong Chen, Pui-In Mak, Stefano D'Amico, Li Zhang, He Qian, and Yan Wang, "A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability," IEEE Transactions on Circuits and Systems – II, vol. 60, no. 11, pp. 761-765, Nov. 2013.  

J7. Yong Chen, Pui-In Mak, Li Zhang, He Qian, and Yan Wang, "0.013mm2, kHz-to-GHz-Bandwidth, Third-Order All-Pole Lowpass Filter with 0.52-to-1.11 pW/pole/Hz Efficiency," IET Electronics Letters, vol. 23, no. 5, pp. 978-982, May 2013. [In Brief]

J6. Yong Chen, Pui-In Mak, Li Zhang, He Qian, and Yan Wang, "Pre-Emphasis Transmitter (0.007mm2, 8Gbit/s, 0-14dB) with Improved Data Zero-Crossing Accuracy in 65nm CMOS," IET Electronics Letters, vol. 49, no. 15, pp. 929-930, Jul. 2013. [In Brief]

J5. Yong Chen, Pui-In Mak, Li Zhang, He Qian, and Yan Wang, "A 0.0012mm2, 8mW, Single-to-Differential Converter with <1.1% Data Cross Error and <3.4ps RMS Jitter up to 14Gb/s Data Rate," IET Electronics Letters, vol. 49, no. 11, pp. 692-694, May 2013.

J4. Yong Chen, Pui-In Mak, Li Zhang, He Qian, and Yan Wang, "A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-μW/Pole/MHz Efficiency, and 0.13-mm2 Die Size in 90-nm CMOS," IEEE Transactions on Circuits and Systems – II, vol. 60, no. 1, pp. 11-15, Jan. 2013.  

J3. Yong Chen, Pui-In Mak, Li Zhang, and Yan Wang, "A 0.07mm2, 2mW, 75MHz-IF, 4th-Order BPF Using a Source-Follower-Based Resonator in 90nm CMOS," IET Electronics Letters, vol. 48, no. 10, pp. 552-554, May 2012.  

J2. Yong Chen, Pui-In Mak, and Yumei Zhou, "Self-Tracking Charge Pump for Fast-Locking PLL," IET Electronics Letters, vol. 46, no. 11, pp. 755-757, May 2010.

J1. Yong Chen, Pui-In Mak, and Yumei Zhou, "Mixed-Integrator Biquad for Continuous-Time Filters," IET Electronics Letters, vol. 46, no. 8, pp. 561-563, Apr. 2010. [In Brief] 

Conference Papers (Total: 50)

C50. Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, and Liyuan Liu, “A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Scoring 231.5-fsrms Clock Jitter and 0.21-pJ/Bit Energy Efficiency in 40-nm CMOS,” IEEE Symposium on VLSI Technology and Circuits, pp. xxxx-xxxx, Jun. 2023.  

C49. Yunbo Huang, Yong Chen, Chaowei Yang, Pui-In Mak, and Rui P. Martins, “A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. xxxx-xxxx, May 2023.  

C48. Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Yong Chen, and Bo Zhao, “A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74µW/Channel and 0.038mm2/Channel by Noise- Orthogonalizing and Pad-Sharing Techniques,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-2, Apr. 2023.  

C47. Zhao Zhang , Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Liyuan Liu, and Nanjian Wu, “A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fs RMS Jitter, -253.8dB Jitter-Power FoM and -76.1dB Spur,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 86-88, Feb. 2023. [Chip Olympics] 

C46. Hao Guo, Yong Chen, Yunbo Huang, Pui-In Mak, and Rui P. Martins, “An 83.3-to-104.7GHz Harmonic- Extraction VCO Incorporating Multi-resonance, Multi-core and Multi-mode (3M) Techniques Achieving -124dBc/Hz Absolute Phase Noise and 190.7dBc/Hz-FOMT,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 152-154, Feb. 2023. [Chip Olympics] 

C45. Xuefeng Li, Yuting Wang, Tianxiang Wu, Yong Chen, Junyan Ren, and Shunli Ma, “A 12.87-dB Gain 10.5-dBm OP1dB 60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime&Asia), pp. 5-9, Nov. 2022. 

C44. Zhonghao Sun, Zhili Liu, Tianxiang Wu, Hao Yu, Yong Chen, and Shunli Ma, “A 33-37GHz Two-Path Power Amplifier with >18-dB Gain and 26.7-dBm Psat in 150nm GaAs process,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime&Asia), pp. 64-67, Nov. 2022. 

C43. Luyao Wang, Tianxiang Wu, Wenyang Liu, Yong Chen, Junyan Ren, and Shunli Ma, “A 32-38GHz Full-360° Low-Phase-Error 6-bit Passive Phase Shifter in 0.15µm GaAs,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime&Asia), pp. 35-39, Nov. 2022. 

C42. Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, and Shunli Ma, “A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19-dBm Output Power and 24.4% Peak PAE,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 560-564, Nov. 2022. 

C41. Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, and Zhao Zhang, “A 0.006-mm2 6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 556-559, Nov. 2022. 

C40. Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, and Zhao Zhang, “A 0.004-mm2  0.7-V 31.654-µW BPSK Demodulator Using a Dual-Path Loop Self-Biased PLL,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 569-573, Nov. 2022. 

C39. Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, and Shunli Ma, “A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15μm GaAs pHEMT Process,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 337-340, Nov. 2022. 

C38. Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, and Nan Qi, “A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O System in 45nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 360-363, Nov. 2022. 

C37. Xudong Wang, Geng Li, Jiacong Sun, Huanjie Fan, Yong Chen, and Hailong Jiao, “Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 246-250, Nov. 2022. 

C36. Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, and Rui P. Martins, “A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector,” IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1-7, Oct. 2022.   

C35. Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, and Rui P. Martins, “A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4, Oct. 2022.   

C34. Shunli Ma, Tianxiang Wu, Zhuofan Xu, Zhonghao Sun, Xuefeng Li, Lei Wu, Biao Hu, Junyan Ren, Yong Chen, and Jiebin Pan, “A 140GHz 4TX-4RX Phased-Array FMCW-FSK Antenna-Packaged Radar Chipset With 25dBm EIRP and 16GHz BW,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1-3, Nov. 2022.   

C33. Guanjie Gu, Changgui Yang, Zhuhao Li, Xiangdong Feng, Ziyi Chang, Ting-Hsun Wang, Yunshan Zhang, Yuxuan Luo, Hong Zhang, Ping Wang, Sijun Du, Yong Chen, and Bo Zhao, “A 2m-Range 711µW Body Channel Communication Transceiver Featuring Dynamically-Sampling Bias-Free Interface Front End,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 10-12, Nov. 2022.   

C32. Yong Chen, Pui-In Mak, Chirn Chye Boon, and Rui P. Martins, “A 2-mW 0.3-to-1GHz Wide-Injection-Locking Multi-mode Transmitter with a 1-Mb/s Data Rate,” IEEE International Conference on Circuits and Systems (ICCS), pp. 195-199, Sep. 2022.  

C31. Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Taiyang Fan, Zhang Qiu, Wenbo Xiao, Yong Chen, and Quan Pan “A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link,” Proc. of 48th European Solid-State Circuits Conference (ESSCIRC), pp. 497-500, Sep. 2022.

C30. Paolo Crovetti, Roberto Rubino, Pedro Toledo, Francesco Musolino, Hamilton Klimach, Yong Chen, and Anna Richelli, “A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification,” Proc. of 48th European Solid-State Circuits Conference (ESSCIRC), pp. 405-408, Sep. 2022.

C29. Tingxun Wang, Zhuhao Li, Bo Liang, Yu Cai, Zhiyu Wang, Changgui Yang, Yuxuan Luo, Jiabao Sun, Xuesong Ye, Yong Chen, and Bo Zhao, “A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor,” IEEE Engineering in Medicine & Biology Society (EMBC), pp. 4626-4630, Jul. 2022.  

C28. Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, and Shunli Ma, “A 124-152 GHz >15-dBm Psat 28-nm CMOS PA Using Chebyshev Artificial-Transmission-Line-Based Matching for Wideband Power Splitting and Combining,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 187-190, Jun. 2022.  

C27. Xin Hu, Yuxuan Luo, Yong Chen, and Bo Zhao, “A Flexible-Window Filtering Technique for Interference Suppression in SpO2 Monitoring,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2463-2466, May 2022.  

C26. Ziyi Chang, Changgui Yang, Yunshan Zhang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Yong Chen, and Bo Zhao, “A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting, ” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-2, Apr. 2022.  

C25. Mingyang You, Minjia Chen, Yihong Li, Guike Li, Liyuan Liu, Yong Chen, Yingtao Li and Nan Qi, “A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects,” IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp. 253-254, Nov. 2021. 

C24. Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, and Nan Qi, “A 4x25Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects,” IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp. 255-256, Nov. 2021. 

C23. Yao Li, Yiqiang Zhao, Mao Ye, and Yong Chen, “A CMOS Readout Circuit for Tactile Sensor Array Using Crosstalk Suppression and Non-uniformity Compensation Techniques,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 181-184, Nov. 2021.

C22. Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, and Nan Qi, “A 100-Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 253-256, Nov. 2021. 

C21. Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, and Shunli Ma, “A 3-to-78GHz Differential Distributed Amplifier with Distributed Balun and Gain Boosting Techniques in 65-nm CMOS Technology,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1-3, Nov. 2021.  

C20. Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Jin Wu, Lei Zhou, and Xinyu Liu, “A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS,” Proc. of 47th European Solid-State Circuits Conference (ESSCIRC), pp. 527-530, Sep. 2021.

C19. Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, and Junyan Ren, “A 35-to-50GHz CMOS Low-Noise Amplifier with 23.5% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio,” Proc. of 47th European Solid-State Circuits Conference (ESSCIRC), pp. 195-198, Sep. 2021.  

C18. Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, “A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 131-134, Jun. 2021. [Best Student Paper Award] 

C17. Yunbo Huang, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2021.  

C16. Xiaoteng Zhao, Yong Chen, Xuqiang Zheng, Pui-In Mak, and Rui P. Martins, “A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase,” IEEE International Microwave Symposium (IMS), pp. 386-388, Jun. 2021. 

C15. Hao Guo, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 294-296, Feb. 2021. [Chip Olympics] 

C14. Yong Chen, Pui-In Mak, Chirn Chye Boon, and Rui P. Martins, “A 0.024-mm2 43-GHz BW Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 687-690, Aug. 2020.  

C13. Hao Guo, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.082mm2 24.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3 PN Corner,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 235-238, Aug. 2020.  

C12. Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS, ” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Mar. 2020.  

C11. Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 229-232, Nov. 2019.  [Best Paper Award]

C10. Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, and Rui P. Martins, “Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 153-156, Nov. 2019.  

C9. Arya Balachandran, Yong Chen, and Chirn Chye Boon, “A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE plus LFEQ, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 221-224, Nov. 2019.  

C8. Zunsong Yang, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 283-284, Nov. 2019.   

C7. Hao Guo, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 410-412, Feb. 2019. [Chip Olympics]  

C6. Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, and Rui P. Martins, “A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 270-272, Feb. 2019. [Chip Olympics]

C5. Yong Chen, Pui-In Mak, Jiale Yang, Ruifeng Yue, and Yan Wang, “Comparator with Built-In Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC,” International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1-4, Jul. 2015.  

C4. Zhaorui Wang, Yong Chen, and He Qian, “A 1.5GS/s 6bit 2bit/step Asynchronous Time Interleaved SAR ADC in 65nm CMOS,” China Semiconductor Technology International Conference (CSTIC), Jan. 2012.

C3. Jiale Yang, Yong Chen, He Qian, Yan Wang, and Ruifeng Yue, “A 3.65mW 5bit 2GS/s Flash ADC with Built-In Reference Voltage in 65nm CMOS process,” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.1-3, Oct. 2012.

C2. Yong Chen, Pui-In Mak, and Yumei Zhou, "Source-Follower-Based Biquad Cell for Continuous-Time Zero-Pole Type Filters," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3629-3632, May 2010.  

C1. Yong Chen and Yumei Zhou, “A Low Power CMOS Mixed-Integrator-Based Continuous-Time Filter,” IEEE International Conference on ASIC (ASICON), pp.274-276, Oct. 2009.