A. N. Bhat, P. Mateman, Z. Xu, P. Vis, P. Detterer, G. K. Ramachandra, Y. Baykal, M. Konijnenburg, Y-H. Liu, C. Bachmann, P. Zhang, "A 7.6-mW IR-UWB Receiver Achieving − 17-dBm Blocker Resilience With a Linear RF Front-End", IEEE JSSC, vol. 59, no. 12, pp. 3993-4008, Dec. 2024.
M. Osada, Z. Xu, Z. Yang and T. Iizuka, "A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering," in IEEE JSSC, vol. 59, no. 7, pp. 2171-2184, July 2024 (Open Access).
M. Miyahara, Z. Xu, T. Ishii, N. Kimura, "A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications", IEICE Trans. Electronics, Vol.E106-C, No.10, pp.521-528, Oct. 2023.
M. Osada, Z. Xu, R. Shibata, and T. Iizuka, "Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation," in IEEE TCAS-I, vol. 69, no. 12, pp. 5072-5084, Dec. 2022 (Open Access).
Z. Xu, "A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection with Dithering-Assisted Local Skew Calibration," IEEE JSSC, vol. 57, no. 10, pp. 2979-2987, Oct. 2022 (Open Access).
S. Li, N. Ojima, Z. Xu, and T. Iizuka, ``Analysis and Simulation of MOSFET-Based Gate-Voltage-Independent Capacitor,'' Japanese Journal of Applied Physics (JJAP), , vol. 61, no. 064501, May 2022. (Open Access)
R. Iwashita, Z.Xu, M. Osada, and T. Iizuka, "A Fractional-N MASH2-k FDC PLL Architecture Enabling Higher-Order Quantisation Noise Shaping", IET Electronics Letters, vol. 58, No. 7, pp. 274 - 276, Mar. 2022. (Open Access)
S. Li, Z. Xu, and T. Iizuka, "Analysis of strong-arm comparator with auxiliary pair for offset calibration", Springer Journal of Analog Integrated Circuits and Signal Processing, vol. 110, no. 3, pp. 535 - 546, Mar. 2022. (Open Access)
Z. Xu, N. Ojima, S. Li, and T. Iizuka, “An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC”, IEEE TVLSI, vol. 29, no. 12, pp. 2153-2162, Dec. 2021. (Open Access)
M. Osada, Z. Xu, and T. Iizuka, "A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –65 dBc In-Band Fractional Spur", IEEE SSC-L, vol. 3, pp. 534-537, 2020. (Open Access) (VDEC Design Award)
Z. Xu, N. Kimura, K. Okada, and M. Miyahara, “ Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator”, IEEE SSC-L, Vol. 3, pp. 274-277, 2020. (Open Access)
J. Wang, T. Iizuka, Z. Xu, T. Nakura, “A Compact Quick-Start Sub-mW Pulse-Width-Controlled PLL with Automated Layout Synthesis using a Place-and-Route Tool”, IEICE Electronics Express, Vol.16, No.19, pp. 1-6, 2019. (Open Access)
Z. Xu, A. Firdauzi, M. Miyahara, K. Okada, and A. Matsuzawa, “Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector”, IEICE Trans. Electronics, Vol.E102-C, No.7, pp.520-529, Jul. 2019.
Y. Fukuda, Z. Xu, and T. Kawahara, "Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error", IEICE Trans. Electronics, Vol.E100-C, No.12, pp.1118-1121, Dec. 2017.
M. Sugawara, Z. Xu, A. Matsuzawa, "Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs", IEICE Trans. Electronics, Vol.E100-C,No.6,pp.576-583, Jun. 2017.
A. Firdauzi, Z. Xu, M. Miyahara, A. Matsuzawa, "High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator", IEICE Trans. Electronics, Vol.E100-C,No.6,pp.548-559, Jun. 2017.
Z. Xu, T. Kawahara, "A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design", IEICE Trans. Electronics, Vol.E100-C, No.4, pp.370-372, Apr.2017.
M. Sugawara, K. Mori, Z. Xu, M. Miyahara, K. Okada, and A. Matsuzawa, "Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell", IEICE Trans. Fundamentals., Vol.E99-A, No.12, pp.2435-2443, Feb.2016.
Z. Xu, M. Miyahara, K. Okada, and A. Matsuzawa, “A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC”, IEEE JSSC, Vol.51, pp. 2345-2356, Oct. 2016. (Yasujiro Niwa Outstanding Paper Award) (Open-Access)
Z. Xu, S. Lee, M. Miyahara, A. Matsuzawa, “Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC”, IEICE Trans. Fundamentals., Vol.E98-A, No.2, pp. 476-484, Feb. 2015.
Z. Xu, M. Miyahara, and A. Matsuzawa, "Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC," IEEE Trans. Nuclear Science, Vol. 61, No. 2, pp. 852-859, Apr. 2014. (Open-Access)
J. G. Lee, Z. Xu, and S. Masui, “Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers”, IEICE Trans. Fundamentals., Vol. E95-A, No.8 pp.1337-1346, Aug. 2012.
Z. Xu, J. G. Lee, S. Masui, “Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL”, IEICE Trans. Electronics, Vol. E94-C, No. 6, pp.1065-1068, Jun. 2011. (VDEC Design Award)
Z. Xu, E. Allebes, P. Mateman, J. van den Heuvel, S. van der Ven, S. Traferro, A. Kumar, R. Li, S. Nagata, K. Bunsen, T. Matsumoto, and M. Konijnenburg, "A 2.3-15.8-GHz 8-Phase Injection-Ripple-Filtered Multi-Ring-Coupled DCO Enabling a Wideband Digital PLL", IEEE VLSIC, Jun. 2025, to be presented.
A. N. Bhat, E. Allebes, E. Bechthum, Z. Xu, J. van Den Heuvel, P. van Zeijl, P. Mateman, S. van der Ven, M. Eskiyerli, S. Traferro, M. El Soussi, A. Farsaei, E. Tiurin, M. Zhou and S. Gamage... "An IEEE802.15.4ab/a/z Compatible IR-UWB 2TRX with Dual-Antenna Full-Duplex 1x3 SIMO Radar Sensing and Aliasing Suppressing Semi-Synchronous TX", IEEE VLSIC, Jun. 2025, to be presented.
A. N. Bhat, P. Mateman, Z. Xu, P. Vis, P. Detterer, G. K. Ramachandra, Y. Baykal, M. Konijnenburg, Y-H. Liu, C. Bachmann, P. Zhang, "A 7.6mW IR-UWB Receiver Achieving −13dBm Blocker Resilience with a Linear RF Front-End", IEEE ISSCC, Feb. 2024.
M. Osada, Z. Xu, and T. Iizuka, "An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering," IEEE ESSCIRC, Sep. 2022.
Z. Yang, Z. Xu, M. Osada, and T. Iizuka, "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter", IEEE VLSIC, Jun. 2022.
R. Shibata, Z. Xu, Y. Hotta, H. Tabata, and T. Iizuka, "A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal", IEEE ISCAS, May 2022.
Z. Xu, N. Ojima, S. Li, and T. Iizuka, "An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC", IEEE ISCAS, May 2022.
Z. Xu, “A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref”, IEEE A-SSCC, pp. 1-3, Busan, Nov. 2021. (Invited to IEEE JSSC 2022)
Z. Xu, N. Kimura, K. Okada, and M. Miyahara, “Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator”, Special Session of IEEE ESSCIRC 2020, Virtual, Sep. 2021.
Z. Xu, N. Kimura, K. Okada, and M. Miyahara, “A 24-MHz 13-μW CTGS Class-C Complementary Colpitts Crystal Oscillator with On-Chip Background Temperature Compensation”, JJAP SSDM, Sep. 2021.
Z. Xu, M. Osada, and T. Iizuka, "A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur", pp. 1-2, IEEE VLSIC, Virtual, Jun. 2021.
M. Osada, Z. Xu, and T. Iizuka, "A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur", pp. 1-2, IEEE VLSIC, Virtual, Jun. 2020.
N. Ojima, Z. Xu, and T. Iizuka, “A 0.0053-mm2 6-Bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65nm CMOS”, IEEE NEWCAS, pp. 1--4 , Munich, Germany, Jun. 2019. (VDEC Design Award)
B. Liu, Y. Zhang, J. Qiu, W. Deng, Z. Xu, H. Zhang, J. Pang, Y. Wang, R. Wu, T. Someya, A. Shirane, and K. Okada, “An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator Based Frequency Synthesizer and Digital Background EVM Calibration”, IEEE CICC, pp. 1-4, Austin, U.S., Apr. 2019.
Z. Xu, A. Firdauzi, M. Miyahara, K. Okada, and A. Matsuzawa, "A 2 GHz 3.1 mW Type-I Digital Ring-Based PLL", IEEE ESSCIRC, pp. 205-208, Lausanne, Switzerland, Sep. 2016.
A. Firdauzi, Z. Xu, M. Miyahara, and A. Matsuzawa, “A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time to Digital Converter Using Charge-Pump and SAR ADC”, IEEE ISCAS, pp. 57-60, Montreal, Canada, May, 2016.
Z. Xu, M. Miyahara, and A. Matsuzawa, “A 3.6 GHz Fractional-N Digital PLL Using SAR-ADC-Based TDC with -110 dBc/Hz In-Band Phase Noise”, IEEE A-SSCC, pp. 321-324, Xiamen, China, Nov. 2015. (Invited to IEEE JSSC 2016.)
Z. Xu, M. Sugawara, M. Miyahara, and A. Matsuzawa, “A 0.8 ps-LSB, 10-bit, 0.018 mm2 Time-to-Digital Converter”, JJAP SSDM, pp. 960-961, Tsukuba, Japan, Sep. 2014.
Z. Xu, M. Sugawara, K. Mori, M. Miyahara, and A. Matsuzawa, “A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm2 Area, and 6.7 kHz Frequency Resolution”, JJAP SSDM, pp. 986-987, Tsukuba, Japan, Sep. 2014.
J. Lin, Z. Xu, M. Miyahara, and A. Matsuzawa, “A 0.5-to-1 V 9-Bit 15-to-90 Ms/S Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier”, IEEE A-SSCC, pp. 85-88, KaoHsiung, Taiwan, Nov. 2014.
Z. Xu, S. J. Lee, M. Miyahara, and A. Matsuzawa, “A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using Charge Pump and SAR-ADC”, IEEE CICC, pp. 1-4, San Jose, USA, Sep. 2013. (Student Scholarship Award)
Z. Xu, M. Miyahara, and A. Matsuzawa, “A 1ps-Resolution Integrator-Based Time-to-Digital Converter Using a SAR-ADC in 90nm CMOS”, IEEE NEWCAS, pp. 1-4, Paris, France, Jun. 2013. (Best Student Paper Award)
Z. Xu, M. Miyahara, and A. Matsuzawa, “ISSCC Student Research Preview”, IEEE ISSCC (Poster Presentation), pp. 512, San Francisco, U.S., Feb. 2013.
Z. Xu, J. G. Lee, and S. Masui, “Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL”, JJAP SSDM, pp. 339-340, Tokyo, Japan, Sep. 2010.
Tetsuya Iizuka, Zule Xu, Zunsong Yang, "Phase-Locked Loop Circuits and Cascaded Phase-Locked Loop Circuits Using It,", Japan Patent Application No. 2023-008347.
Tetsuya Iizuka, Zule Xu, Masaru Osada, "Fractional Phase Locked Loop Circuits and Phase Locked Loop Circuit Devices,", Japan Patent Application No. 2019-192731.