About Me

Assistant Professor / Lecturer @ The University of Tokyo

VLSI Design and Education Center

2-11-16 Yayoi, Bunkyo-ku, Tokyo, 113-0032, Japan

Education

  • 2011. 4 -- 2015. 4 Doctor of Philosophy, Department of Physical Electronics, Tokyo Institute of Technology, Japan

Thesis: Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer

  • 2009. 4 -- 2011. 3 Master of Engineering, Department of Electrical Communication, Tohoku University, Japan

  • 2002. 10 -- 2006. 7 Bachelor of Engineering, Department of Electronic Engineering, Dalian University of Technology, China

Employment

  • 2019. 10 -- present Assistant Professor / Lecturer (特任講師), Systems Design Lab (d.lab), The University of Tokyo, Japan

  • 2018. 4 -- 2019. 9 Assistant Professor / Lecturer (特任講師), VLSI Design and Education Center, The University of Tokyo, Japan

  • 2016. 4 -- 2018. 3 Assistant Professor, Department of Electrical Engineering, Tokyo University of Science, Japan

  • 2015. 4 -- 2016. 4 Research Staff (Postdoc), Department of Physical Electronics, Tokyo Institute of Technology, Japan

  • 2006. 8 -- 2008. 8 Hardware Engineer, Beijing Infomedia Co. Ltd., China

Awards

  • 2017 Yasujiro Niwa Outstanding Paper Award (丹羽保次郎記念論文賞)

  • 2013 IEEE Custom Integrated Circuits Conference (CICC): Student Scholarship Award

  • 2013 IEEE International New Circuits And Systems Conference (NEWCAS): Best Student Paper Award

  • 2011 VLSI Design and Education Center (VDEC) Designer's Forum Award

Activities

  • Technical Program Committee Member, IEEE Asian Solid-State Circuits Conference (2018 - present)

  • Associate Editor, IEICE Special Section on Analog Circuits and Their Application Technologies (2017 - present)

  • Associate Editor, Solid-State Circuit Design-Architecture, Circuit, Device and Design Methodology (2019 - present)

  • 電子情報通信学会(IEICE) 集積回路研究専門委員会(ICD) 専門委員 (Committee Member) (2017 - present)