MTech Dissertation: SAT Solver based Multi-Cycle Droop Fault Testing
Duration: August 2008 - July 2009
Guide: Dr Susmita Sur-Kolay, ACM Unit, Indian Statistical Institute, Kolkata
Project Details :
Formulated a fault model for Multi-Cycle Power Droop in VLSI circuits.
Developed an algorithm to detect such faults and transformed it into domain of Boolean Satisfiability (SAT).
Implemented ATPG using open-source SAT-solver zchaff which yielded promising results on industrial benchmarks for combinational and full-scan circuits.
This was chosen as the Best Dissertation in the graduating batch for M.Tech(CS), 2009. (PDF)
XML Validator
Duration: December 2008 - January 2009
Project Details:
The requirement was to verify that whether an input xml file is conforming to the specifications laid down in the DTD file (also to be taken as input).
The XML/DTD files could be arbitrarily large, and include as many elements as the user wished. When executed, the program would print out the a vertical ASCII formatted XML tree, and also state whether or not it matched the specifications laid down by the DTD.
The entire project was implemented in C++ (C++03), without using any third party libraries such as Boost.