Note: this section will not cover the Gain, Noise Cancelation, or use of multiple channels. See the ADC section of Atmega324p's datasheet.
ADMUX: ADC Multiplexer Selection Register
REFS0 and REFS1
The table below show how to set the REFs bits. The UART - Serial Communication How To is using AREF.
ADLAR
ADC Left Adjust Result. Set this to one to left align the conversion bits in the ADCH/ADCL register. The UART - Serial Communication How To leaves this in the default right align configuration. See the datasheet for details on potential data loss and other specifics to alignment of the conversion result.
ADLAR = 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ADLAR = 1
MUX0 - 4
Analog channel (and gain) selection bits. The following table provides the 8 five-bit values for selecting the channels. The UART - Serial Communication How To uses channel 0. These channels correspond to the physical pins 20 - 27 on the Atmega324p.
ADCSRA - ADC Control and Status Register A
ADCSRB - ADC Control and Status Register B
ADCL & ADCH - ADC Low and High Order Bits (of the Converted Value)
The ADCL & ADCH registers together are 16 bits, ten of which are used for the final ADC conversion value of the analog input. The ADLAR bit in the ADCSRA register can be used to make this conversion value left or right aligned. By default the values will be right aligned.
It is critical the ADCL bits are read first then the ADCH bits when reading conversion results if the values are right aligned to avoid losing the conversion result. For more details on this see the datasheet for General Operation of the ADC. If the values are left aligned and only bits are required for precision, then it is sufficient to only read the ADCH. The UART - Serial Communication How To uses the right aligned values and reads the ADCL first.
Initial values are 0.
ADCH
15 14 13 12 11 10 9 8
ADCL
7 6 5 4 3 2 1 0
DIDR0 - DigitalInput Disable
ADPS2-0 - Prescaler selection
The table shows the first four division factors for the prescaler. See the datasheet for the remaining division factors. Because we are using a relatively slow system clock of 1MHz we want the division factor low when creating the ADC clock frequency. For this reason, we set all the values for these three registers to 0.