Contributions

Issued Patent

1. US11177207, B2, Compact transistor utilizing shield structure arrangement, Shilimkar, Vikas, Kim, Kevin, Lessard, Charles John, Kabir, Humayun

2. CN106169470, B, Device with conductive feature formed on cavity and corresponding method, Green, Bruce M., Huang, Jenn Hwa, Shilimkar, Vikas S.

3. EP3624186, B1, Electromagnetically-shielded microelectronic assemblies, Srindhi, Embar Ramanujam, Shilimkar, Vikas, Viswanathan, Lakshminarayan

4. EP3327774, B1, Device with a conductive feature formed over a cavity and method therefor, Green, Bruce Mcrae, Huang, Jenn Hwa, Shilimkar, Vikas

5. US10861774, B2, Internally-shielded microelectronic packages and methods for the fabrication thereof, Sanchez, Audel, Viswanathan, Lakshminarayan, Shilimkar, Vikas, Srinidhi Embar, Ramanujam

6. US10672703, B2, Transistor with shield structure, packaged device, and method of fabrication, Shilimkar, Vikas, Kim, Kevin, Rueda, Hernan, Kabir, Humayun

7. US10629518, B2, Internally-shielded microelectronic packages and methods for the fabrication thereof, Sanchez, Audel, Viswanathan, Lakshminarayan, Shilimkar, Vikas, Srinidhi Embar, Ramanujam

8. US10574198, B2, Integrated circuit devices with selectively arranged through substrate vias and method of manufacture thereof, Shilimkar, Vikas, Lamey, Daniel Joseph, Kim, Kevin

9. US10506704, B1, Electromagnetically-shielded microelectronic assemblies and methods for the fabrication thereof, Embar, Ramanujam Srinidhi, Shilimkar, Vikas, Viswanathan, Lakshminarayan

10. US10228756, B2, Voltage regulator having circuit to control super capacitor, Shilimkar, Vikas S., Nguyen, Don J., Gurumoorthy, Nagasubramanian N.

11. US9871107, B2, Device with a conductive feature formed over a cavity and method therefor, Green, Bruce M., Huang, Jenn Hwa, Shilimkar, Vikas S.

12. TWI578661, B, Power supply apparatus, method and system, Shilimkar, Vikas S, Nguyen, Donald J, Gurumoorthy, Nagasubramanian

13. TWI561950, B, Voltage regulator, Shilimkar, Vikas, Nguyen, Don, Gurumoorthy, Nagasubraman

14. US9477278, B2, Voltage regulator, Shilimkar, Vikas S., Nguyen, Don J., Gurumoorthy, Nagasubramanian N.

15. US9246340, B2, Battery pack, Shilimkar, Vikas S., Nguyen, Donald J., Gurumoorthy, Nagasubramanian

16. CN103890681, B, Voltage regulator, electronic equipment and be the method for power electronic equipment, Shilimkar, Vikas, Nguyen, Don, Gurumoorthy, Nagasubraman

Patent Pending

1. US20210242840, A1, Compact rfic with stacked inductor and capacitor, Shilimkar, Vikas, Kim, Kevin, Schultz, Joseph Gerard

2. US20210225784, A1, Rf amplifiers with series-coupled output bondwire arrays and shunt capacitor bondwire array, Shilimkar, Vikas, Kim, Kevin, Sweeney, Richard Emil, Johnson, Eric Matthew

3. EP3852270, A1, Rf amplifiers with series-coupled output bondwire arrays and shunt capacitor bondwire array, Shilimkar, Vikas, Kim, Kevin, Sweeney, Richard Emil, Johnson, Eric Matthew

4. CN113141162, A, Rf amplifier with series coupling output bonding wire array and parallel capacitor bonding wire array, Shilimkar, Vikas, Kim, Kenny, Sweeney, Richard Emil, Johnson, Eric Matthew

5. US20210193569, A1, Compact transistor utilizing shield structure arrangement, Shilimkar, Vikas, Kim, Kevin, Lessard, Charles John, Kabir, Humayun

6. CN110957302, A, Transistor with shielding structure, packaging device and manufacturing method thereof, Shilimkar, Vikas, Kim, Kevin, Rueda, Hernan, Kabir, Humayun

7. EP3629373, A1, Transistor with shield structure, packaged device, and method of fabrication, Shilimkar, Vikas, Kim, Kevin, Rueda, Hernan, Kabir, Humayun

8. EP3621108, A1, Internally-shielded microelectronic packages and methods for the fabrication thereof, Sanchez, Audel, Viswanathan, Lakshminarayan, Shilimkar, Vikas, Srinidhi, Embar Ramanujam

9. CN110875283, A, Internally shielded microelectronic packages and methods of making same, Sanchez, Audel, Viswanathan, Lakshminarayan, Shilimkar, Vikas, Srinidhi, Embar Ramanujam

10. CN110854105, A, Electromagnetically shielded microelectronic assembly and method of making same, Srindhi, Embar Ramanujam, Shilimkar, Vikas, Viswanathan, Lakshminarayan

11. EP3327774, A1, Device with a conductive feature formed over a cavity and method therefor, Green, Bruce Mcrae, Huang, Jenn Hwa, Shilimkar, Vikas

12. TW201432407, A, Voltage regulator, Nguyen, Don, Shilimkar, Vikas

13. DE112011105699, T5, Voltage regulators, Shilimkar, Vikas, Nguyen, Don, Gurumoorthy, Nagasubraman

Journals

1. E. Westberg, J. Staudinger, J. Annes, and V. Shilimkar, “5G Infrastructure RF Solutions: Challenges and Opportunities,” Microwave Magazine Focus Issue, December 2019.

2. V. S. Shilimkar; A. Weisshaar, "Modeling of Metal-Fill Parasitic Capacitance and Application to On-Chip Slow-Wave Structures," in IEEE Transactions on Microwave Theory and Techniques , vol. xx, no.99, pp.1-9

3. “Intel 945GMS Express Chipset for Small Form Factor Platform Based on Intel Centrino Duo Mobile Technology,” Intel Technology Journal, Volume 10, Issue2, 2006. [link]

Conference Proceedings

1. V. Shilimkar and K. Kim, "RF LDMOS Transistor Plastic Immunity Enhancement in Power Amplifier Module for 5G Applications," IEEE BiCMOS and Compound Semiconductor Integrated Circuits Technology Symposium (BCICTS), 2021

2. V. Shilimkar, H. Kabir, L. Zhang, A. Mahan, and K. Kim, "Equivalent Circuit Modeling of On-Chip Inductors using Feature-based Optimization," accepted for IEEE Topical Meetings on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Austin, 2016

3. H. Kabir, V. Shilimkar, L. Zhang, and K. Kim, "Large Space Spiral Inductor Parametric Model Develoment Technique for RFIC Design," IEEE Numerical Electromagnetic and Multi-physics Modeling and Optimization (NEMO) conference, Canada, 2015

4. L. Zhang, H. Rueda, D. Lamey, H. Kabir, V. Shilimkar, and K. Kim, "Substrate Optimization for Accurate EM Simulation," IEEE Numerical Electromagnetic and Multi-physics Modeling and Optimization (NEMO) conference, Canada, 2015

5. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “ Scalable Modeling of On-chip Spiral Inductors including Metal Fill Parasitics,” IEEE 62th International Microwave Symposium, Florida, USA, 2014 [pdf].

6. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, "Broadband Characterization of Onchip RF Spiral Inductor using Multi-line TRL Calibration," accepted for presentation at IEEE 82nd ARFTG Microwave Measurement Symposium, 2013 (Best paper award finalist).

7. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, ``Modeling and Characterization of Metal Fill in Radio Frequency Integrated Circuits," SRC TECHCON, Austin, Texas, September 9 – 10, 2013 (Best in Session, 1st Place).

8. S. G. Gaskill, V. S. Shilimkar, and A. Weisshaar, “High-Frequency Modeling of Eddy-Current Loss due to Metal Fill in Integrated Circuits,” accepted for presentation at IEEE European Microwave Integrated Circuits Conference (EuMIC), 2013.

9. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, ``Efficient Modeling of Metal Fill Parasitic Capacitance in On-Chip Transmission Lines,'' IEEE 60th International Microwave Symposium, Montreal, Canada, pp. .[link]

10. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Closed-form Expressions for Modeling Metal Fill Effects in Interconnects,” IEEE 15th Workshop on Signal Propagation on Interconnects, Italy, May 2011, pp. [link]

11. V. S. Shilimkar, D. J. Nguyen, and N. Gurumoorthy, “Light Load Voltage Regulator Efficiency Improvement Using Switched Super-Capacitors,” Intel Techfest Conference, 2011. (Intel Inc. Internal Conference).

12. S. G. Gaskill, V. S. Shilimkar, and A. Weisshaar, “Wide-range closed-form eddycurrent loss formula for metal fill,” IEEE 19th conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 , pp.129-132, Oct. 2010. [link]

13. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Experimental Characterization of Metal Fill Placement and Size Impact on Spiral Inductors,” IEEE 18th Electrical Performance of Electronic Packaging and Systems, USA, 2009, pp. 101-104.(Best student paper award finalist) [link]

14. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Impact of Metal Fill on On-chip Interconnect Performance,” IMAPS 42nd Symposium on Microelectronics, USA, 2009, pp. 983-990. [link]

15. S. G. Gaskill, V. S. Shilimkar, and A. Weisshaar, “Accurate closed-form capacitance extraction formulas for metal fill in RFICs,” IEEE Radio Frequency Integrated Circuits Symposium, USA, 2009, pp.611-614. [link]

16. S. G. Gaskill, V. S. Shilimkar, and A. Weisshaar, “Noise Suppression in VLSI Circuits Using Dummy Metal Fill,” IEEE 12th Workshop on Signal Propagation on Interconnects, Avignon, France, May 2008, pp.1-4. [link]

17. S. G. Gaskill, V. S. Shilimkar, and A. Weisshaar, “Isolation Enhancement in Integrated Circuits Using Dummy Metal Fill,” IEEE Radio Frequency Integrated Circuits Symposium, USA, 2008, pp.483-486. [link]

Presentations/talks

1. V. Shilimkar, H. Kabir, L. Zhang, A. Mahan, and K. Kim, "Equivalent Circuit Modeling of On-Chip Inductors using Feature-based Optimization," accepted for IEEE Topical Meetings on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Austin, 2016

2. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, "Broadband Characterization of Onchip RF Spiral Inductor using Multi-line TRL Calibration," accepted for presentation at IEEE 82nd ARFTG Microwave Measurement Symposium, 2013 (Best paper award finalist).

3. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, ``Modeling and Characterization of Metal Fill in Radio Frequency Integrated Circuits," SRC TECHCON, Austin, Texas, September 9 – 10, 2013(Best in Session, 1st Place).

4. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Efficient Modeling of Metal Fill Parasitic Capacitance in On-Chip Transmission Lines,” IEEE 60th International Microwave Symposium, Montreal, Canada, 2012.

5. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, I“mpact of Metal Fill on On-chip Interconnect Performance,” IMAPS NW Chapter Technical Symposium, Vancouver, WA, USA, Feb. 2010.

6. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Impact of Metal Fill on On-chip Interconnect Performance,” IMAPS 42nd Symposium on Microelectronics, USA, 2009, pp. 983-990.

7. V. S. Shilimkar, S. G. Gaskill, and A. Weisshaar, “Experimental Characterization of Metal Fill Placement and Size Impact on Spiral Inductors,” IEEE 18th Electrical Performance of Electronic Packaging and Systems, USA, 2009, pp. 101-104.(Best student paper award finalist)

8. “Enabling Metal-Fill-Aware Design of RF/Mixed-Signal Integrated Circuits” presented at SRC GRC CADTS LPD review, University of California, Berkeley, Oct.- 2009.

Theses

1. V. S. Shilimkar, “Enabling Metal Fill Aware Design of Integrated Circuits,” PhD thesis, Oregon State University, USA, 2014. [link]

2. V. S. Shilimkar, “Metal Fill Considerations for On-chip Interconnects and Spiral Inductors,” M.S. thesis, Oregon State University, USA, 2009. [link]