A Side Journey to Titan
Thomas Roche, Victor Lomné, Camille Mutschler, Laurent Imbert
Usenix Security 2021
Side-channel Attacks on Blinded Scalar Multiplications Revisited
Thomas Roche, Laurent Imbert, Victor Lomné
CARDIS 2019
An Industrial Outlook on Challenges of Hardware Security in Digital Economy - Extended Abstract
Shivam Bhasin, Victor Lomné, Karim Tobich
SPACE 2017
Cost-Effective Design Strategies for Securing Embedded Processors
Florent Bruguier, Pascal Benoit, Lionel Torres, Lyonel Barthe, Morgan Bourree, Victor Lomné
IEEE Transactions in Emerging Topics Computers 4 (1)
Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes
Christoph Dobraunig, Maria Eichlseder, Thomas Korak, Victor Lomné, Florian Mendel
ASIACRYPT 2016
Side-Channel Attack against RSA Key Generation Algorithms
Aurélie Bauer, Eliane Jaulmes, Victor Lomné, Emmanuel Prouff, Thomas Roche
CHES 2014
How to Estimate the Success Rate of Higher-Order Side-Channel Attacks
Victor Lomné, Emmanuel Prouff, Matthieu Rivain, Thomas Roche, Adrian Thillard
CHES 2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest
Christophe Clavier, Jean-Luc Danger, Guillaume Duc, M Abdelaziz Elaabid, Benoît Gérard, Sylvain Guilley, Annelie Heuser, Michael Kasper, Yang Li, Victor Lomné, Daisuke Nakatsu, Kazuo Ohta, Kazuo Sakiyama, Laurent Sauvage, Werner Schindler, Marc Stöttinger, Nicolas Veyrat-Charvillon, Matthieu Walle, Antoine Wurcker
Journal of Cryptographic Engineering 1-16
Behind the Scene of Side-Channel Attacks
Victor Lomné, Emmanuel Prouff, Thomas Roche
ASIACRYPT 2013
Implementing Lightweight Block Ciphers on x86 Architectures
Ryad Benadjila, Jian Guo, Victor Lomné, Thomas Peyrin
SAC 2013
Fault Attacks on AES with Faulty Ciphertexts Only
Thomas Fuhr, Eliane Jaulmes, Victor Lomné, Adrian Thillard
FDTC 2013
Collision-Correlation Attack against some 1st-order Boolean Masking Schemes in the Context of Secure Devices
Thomas Roche, Victor Lomné
COSADE 2013
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence
Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine
IEEE Transactions VLSI Systems 20(3)
On the Need of Randomness in Fault Attack Countermeasures - Application to AES
Victor Lomné, Thomas Roche, Adrian Thillard
FDTC 2012
Combined Fault and Side-Channel Attack on Protected Implementations of AES
Thomas Roche, Victor Lomné, Karim Khalfallah
CARDIS 2011
Formal Framework for the Evaluation of Waveform Resynchronization Algorithms
Sylvain Guilley, Karim Khalfallah, Victor Lomné, Jean-Luc Danger
WISTP 2011
A Simulation Flow for Time Domain Magnetic Radiations of ICs
Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Thomas Ordas, Mathieu Lisart, Jérome Toublanc
EMC Europe 2010
Modeling Time Domain Magnetic Emissions of ICs
Victor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc
PATMOS 2010
A GALS Pipeline DES Architecture to Increase Robustness against DPA and DEMA Attacks
Rafael Soares, Ney Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres
SBCCI 2010
Differential Power Analysis Enhancement with Statistical Preprocessing
Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert
DATE 2010
Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography
Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert
VLSI-SoC 2009
Magnitude Squared Incoherence EM Analysis for Integrated Cryptographic Module Localisation
Amine Dehbaoui, Victor Lomné, Philippe Maurine, Lionel Torres
Electronic Letters 08/2009
Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA
Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans
DATE 2009
Secure Triple Track Logic Robustness against Differential Power and Electromagnetic Analyses
Victor Lomné, Amine Dehbaoui, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans, Fernando Moraes
Journal of Integrated Circuits and Systems 01/2009
Triple Rail Logic Robustness against DPA
Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans
ReConFig 2008
Evaluating the Robustness of Secure Triple Track Logic through Prototyping
Rafael Soares, Ney Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert
SBCCI 2008