Résumé

Education

• Chonnam National University, South Korea (Sep 2014 - Feb 2018)

  • Ph.D. in Computer Engineering                                                                                         

• Chonnam National University, South Korea (Sep 2012 - Aug 2014)

  • M.S. in Computer Engineering                                                                                            

  • GPA: 94.4/100

• Hanoi University of Science and Technology, Vietnam (Sep 2007 - Jun 2012)

  • B.S. in Electronics and Telecommunications                                                               

  • GPA: 8.02/10                                           

Professional Experience

• Assistant Professor, School of Information and Communications Technology, Hanoi University of Science and Technology, Vietnam (Jun 2020 - present)

• Research Professor, Department of Computer Science & Engineering, Korea University, South Korea (May 2018 - Dec 2019)

  • Explored architectural benefits of the monolithic 3D integration (M3D).

  • Proposed M3D based structures for high-performance, energy-efficient CPUs/GPUs.  

• Research Assistant, School of Electronics & Computer Engineering, Chonnam National University, South Korea (Aug 2012 - Feb 2018)

  • Proposed and evaluated various hardware enhancements (e.g. thread block/warp scheduling, cache bypassing) to improve performance of the GPU architecture for executing general-purpose applications.

  • Proposed and evaluated techniques to improve the accuracy of branch prediction and the performance of cache replacement in the CPU architecture. 

Honors & Awards

• Mobile Device Interface Research Center (under ITRC) Research Fund Sponsorship, South Korea. (2012-2017)

• BK21 (Plus) Research Fund Sponsorship, South Korea. (2012-2016)

• Admission & Scholarship to an M.S./Ph.D. Program in Computer Engineering, Chonnam National University, South Korea.  (2012)

• Admission & Scholarship to an M.S./Ph.D. Integrative Program in Computer Science, POSTECH, South Korea. (2012)

• Admission & Scholarship to an M.S. Program in Electronics & Electrical Engineering, Dongguk University, South Korea. (2012)

• Encouragement Scholarship for Excellent Study Records, Hanoi University of Science and Technology, Vietnam. (2008-2010)

• Second Prize in the Contest for Excellent High School Students of Hanoi City (subject: Physics), Hanoi, Vietnam. (twice, 2006 and 2007)

• First Prize in the Contest for Excellent High School Students of Hanoi City (subject: Chemistry), Hanoi, Vietnam. (2006)

Technical Skills

• Simulators: SimpleScalar, GPGPU-Sim, GPUWattch, Multi2Sim, (Access) Noxim, CACTI, GEM5

• Programming languages: C/C++, CUDA, OpenCL, Python, HTML, NodeJS

• Hardware: HDLs (VHDL, Verilog), FPGA (Altera Quatus II, Xilinx ISE), AutoCAD, Proteus

• Software: Windows/Linux (Ubuntu, Fedora), GNU compiler (gcc), MATLAB, Visual Studio

Professional Services 

• Reviewer of Cell & Elsevier Heliyon, 2024.

• Reviewer of Springer Journal of Supercomputing, 2024.

• Reviewer of Journal of Electronic Science and Technology, 2023.

• Reviewer of the 15th IEEE International Conference on Knowledge and Systems Engineering, 2023.

• Reviewer of Cell & Elsevier Heliyon, 2023.

• Reviewer of Springer Journal of Supercomputing, 2023.

• Reviewer of Elsevier Microprocessors and Microsystems, 2022.

• Reviewer of Springer Journal of Supercomputing, 2022.

• Reviewer of Springer Journal of Supercomputing, 2021.

• Reviewer of Elsevier Microprocessors and Microsystems, 2021.

• Reviewer of Journal of Electronic Science and Technology, 2020.

• Reviewer of Elsevier Microprocessors and Microsystems, 2020.

• Reviewer of the 6th Annual Conference of Vietnamese Young Scientists, 2019.

• Reviewer of Elsevier Microprocessors and Microsystems, 2018.

Research Interests

• High-Performance & Low-Power Architecture; CPU/GPGPU/Multi-core Processor; Embedded Systems; Monolithic 3D based Architecture; Processing in Memory; FPGA & ASIC; AI for IoT

Publications

• ISI/SCOPUS Journal Papers

  • Cong Thuan Do, Cheol Hong Kim, and Sung Woo Chung. "Aggressive GPU Cache Bypassing with Monolithic 3D Based NoC." Springer Journal of Supercomputing (SUPE), vol. 79, no. 5, 2023. [ISI] 

  • Cong Thuan Do, Jeong Hwan Choi, Young Seo Lee, Cheol Hong Kim, and Sung Woo Chung. "Enhancing Matrix Multiplication with a Monolithic 3D Based Scratchpad Memory." IEEE Embedded Systems Letters (ESL), vol. 13, no. 2, 2021. [ISI] 

  • Cong Thuan Do, Hong Jun Choi, Sung Woo Chung, and Cheol Hong Kim. "A Novel Warp Scheduling Scheme Considering Long-Latency Operations for High-Performance GPUs." Springer Journal of Supercomputing (SUPE), vol. 76, no. 4, 2020. [ISI] 

  • Cong Thuan Do, Jong Myon Kim, and Cheol Hong Kim. "Application Characteristics-Aware Sporadic Cache Bypassing for High Performance GPGPUs." Elsevier Journal of Parallel and Distributed Computing (JPDC), vol. 122, 2018. [ISI] 

  • Cong Thuan Do, Jong Myon Kim, and Cheol Hong Kim. "Early Miss Prediction based Periodic Cache Bypassing for High Performance GPUs." Elsevier Microprocessors and Microsystems (MICPRO), vol. 55, 2017. [ISI] 

  • Dong Oh Son, Cong Thuan Do, Hong Jun Choi, Ji Seung Nam, and Cheol Hong Kim. "A Dynamic CTA Scheduling Scheme for Massive Parallel Computing." Springer Cluster Computing (CLUSTER COMPUT), vol. 20, no. 1, 2017. [ISI]

  • Cong Thuan Do, Hong Jun Choi, Dong Oh Son, Jong Myon Kim, and Cheol Hong Kim. "NTB Branch Predictor: Dynamic Branch Predictor for High-Performance Embedded Processors." Springer Journal of Supercomputing (SUPE), vol. 72, no. 5, 2016. [ISI]

  • Cong Thuan Do, Hong Jun Choi, Jong Myon Kim, and Cheol Hong Kim. "A New Cache Replacement Algorithm for Last-Level Cache by Exploiting Tag-Distance Correlation of Cache Lines." Elsevier Microprocessors and Microsystems (MICPRO), vol. 39, no. 4, 2015. [ISI]

• Korean Journal Papers

  • Cong Thuan Do, Gwang Bok Kim, and Cheol Hong Kim. "Workload Characteristics-based L1 Data Cache Switching-off Mechanism for GPUs." Journal of the Korea Society of Computer and Information (JKSCI), vol. 23, no. 10, 2018.

  • Cong Thuan Do, Yong Choi, Jong Myon Kim, and Cheol Hong Kim. "A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization." KIPS Transactions on Computer and Communication Systems (KTCCS), vol. 6, no. 5, 2017.

  • Cong Thuan Do, Dong Oh Son, Jong Myon Kim, and Cheol Hong Kim. "Re-ordering Memory Requests for Improving the Performance of GPUs." Journal of Korean Institute of Next Generation Computing (KINGPC), vol. 12, no. 6, 2016.

  • Cong Thuan Do, Dong Oh Son, Jong Myon Kim, and Cheol Hong Kim. "A New Thread Block Scheduling Technique for Improving the Performance of GPGPU Architecture." Journal of Korean Institute of Next Generation Computing (KINGPC), vol. 11, no. 4, 2015.

  • Cong Thuan Do, Dong Oh Son, Jong Myon Kim, and Cheol Hong Kim. "A New Cache Replacement Policy for Improving Last Level Cache Performance." Journal of KIISE: Computer Systems and Theory (JOK), vol. 41, no. 11, 2014.

• Conference Papers (including LNEE)

  • Cong Thuan Do, Anh Nam Le, Van Duc Nguyen, and Van Chien Trinh, “Deep Learning-based Prediction of Alertness and Drowsiness using EEG Signals.” The 12th ACM International Symposium on Information and Communication Technology (SOICT), Ho Chi Minh City, Vietnam, 2023.

  • Cong Thuan Do, Cheol Hong Kim, and Sung Woo Chung. "A Novel Monolithic 3D Based GPU Cache Architecture." The 37th IEEE International Conference on Computer Design (ICCD), Abu Dhabi, UAE, 2019. (poster) [Paper Acceptance Rate = 32%, 87 oral presentations + 21 posters]

  • Cong Thuan Do, Young Ho Gong, Cheol Hong Kim, Seon Wook Kim, and Sung Woo Chung. "Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency." The 25th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, 2019. [Paper Acceptance Rate = 23%, 39 oral presentations + 16 posters]

  • Cong Thuan Do, Min Goo Moon, Jong Myon Kim, and Cheol Hong Kim. "A Study on L1 Data Cache Bypassing Methods for High-Performance GPUs." The 19th International Conference on Parallel and Distributed Computing: Applications and Technologies (PDCAT), Jeju, South Korea, 2018. 

  • Dong Oh Son, Cong Thuan Do, Hong Jun Choi, Jong Myon Kim, Ji Seung Nam, and Cheol Hong Kim. "A New Pre-fetch Policy for Data Filter Cache in Energy-Aware Embedded Systems." The 7th International Conference on Information Science and Applications (ICISA), Ho Chi Minh City, Vietnam, 2016. (LNEE vol. 376)

  • Dong Oh Son, Cong Thuan Do, Hong Jun Choi, Jong Myon Kim, Jae Hyung Park, and Cheol Hong Kim. "CTA-Aware Dynamic Scheduling Scheme for Streaming Multiprocessors in High-Performance GPUs." The 7th International Conference on Information Science and Applications (ICISA), Ho Chi Minh City, Vietnam, 2016. (LNEE vol. 376)

  • Cong Thuan Do, Hong Jun Choi, and Cheol Hong Kim. "Varying Parameter Configurations on GPU." The Conference on Information and Control Systems, Jeju, South Korea, 2014. 

  • Cong Thuan Do, Jin Sul Kim, In Tae Hwang, Sang Hyo Kim, and Cheol Hong Kim. "A Novel Last-Level Cache Replacement Policy to Improve the performance of Mobile Systems." The Workshop on Mobile and Wireless, Jeju, South Korea, 2014. (Advanced Science and Technology Letters, vol. 46)

  • Cong Thuan Do, Jong Myon Kim, and Cheol Hong Kim. "A Novel Dynamic Branch Predictor for High-Performance Embedded Processors." The FTRA International Symposium on Ubiquitous Computing and Embedded Systems, Danang, Vietnam, 2013. 

Patents

• • Sung Woo Chung, Cong Thuan Do, Young Seo Lee, and Jeong Hwan Choi. "A Monolithic 3D Based Scratchpad Memory (모놀리식 3D 집적 기술 기반 스크래치패드 메모리)." Korean Intellectual Property Office (KIPO),  Registration Number: 10-2443742, September 13, 2022.

  • Sung Woo Chung, Cong Thuan Do, and Young Seo Lee. "A GPU Cache Bypassing Method and Apparatus with the Adoption of Monolithic 3D Based Network-on-Chip (모놀리식 3D 집적 기술 기반 NoC 구조를 활용한 GPU 캐시 바이패스 방법 및 장치)." Korean Intellectual Property Office (KIPO), Registration Number: 10-2340444, December 14, 2021.

  • Sung Woo Chung, Cong Thuan Do, and Jeong Hwan Choi. "Memory Data Transform Method and Computer for Matrix Multiplication (행렬 연산시 메모리 데이터 변환 방법 및 컴퓨터)." Korean Intellectual Property Office (KIPO), Registration Number: 10-2327234, November 10, 2021.

  • Sung Woo Chung, Cong Thuan Do, and Young Seo Lee. "Monolithic 3D Integration based L1 Cache Memory for GPUs (모놀리식 3D 집적 구조 기반 GPU L1 캐시 메모리)." Korean Intellectual Property Office (KIPO), Registration Number: 10-2172556, October 27, 2020.

  • Cheol Hong Kim, Cong Thuan Do, and Yong Choi. "Application Characteristics-Aware Sporadic Cache Bypassing Technique, Streaming Multiprocessor and Embedded System Performed by the Technique (어플리케이션 특성 기반 캐쉬 성능에 따른 주기적인 캐쉬 우회 기법, 그 기법이 적용된 스트리밍 멀티프로세서 및 임베디드 시스템)." Korean Intellectual Property Office (KIPO), Registration Number: 10-1969435, April 10, 2019.

  • Cheol Hong Kim, Cong Thuan Do, and Gwang Bok Kim. "Early Miss Prediction based Periodic Cache Bypassing Technique, Streaming Multiprocessor and Embedded System Performed by the Technique (캐쉬 적중률 예측에 기반한 주기적 캐쉬 우회 기법, 그 기법이 적용된 스트리밍 멀티프로세서 및 임베디드 시스템)." Korean Intellectual Property Office (KIPO), Registration Number: 10-1946476, January 31, 2019.

  • Dong Oh Son, Cong Thuan Do, and Cheol Hong Kim. "Cache Bypassing Technique, Streaming Multiprocessor and Embedded System Performed by the Technique (캐쉬 우회 기법, 그 기법이 적용된 스트리밍 멀티프로세서 및 임베디드 시스템)." Korean Intellectual Property Office (KIPO), Registration Number: 10-1852012, April 19, 2018.

  • Dong Oh Son, Cong Thuan Do, Hong Jun Choi, and Cheol Hong Kim. "Cache Replacement Algorithm for Last-Level Caches by Exploiting Tag-Distance Correlation of Cache Lines and Embedded Systems (캐시 라인의 태그 거리 상관관계를 이용한 캐시 교체 방법 및 임베디드 시스템)." Korean Intellectual Property Office (KIPO), Registration Number: 10-1697515, January 12, 2017.

  • Dong Oh Son, Cong Thuan Do, Hong Jun Choi, and Cheol Hong Kim. "Modified-LRU Replacement Policy, Processor and Embedded System (프로세서 장치의 캐시 교체 방법, 프로세서 장치 및 임베디드 시스템)." Korean Intellectual Property Office (KIPO), Registration Number: 10-1541737, July 29, 2015.

Note: KIPO forms part of the IP5 - a forum of 5 largest intellectual property offices in the world (USPTO, EPO, JPO,  KIPO, and SIPO (now CNIPA)).