I am an Assistant Professor in the AI Computing Research Unit at Tokyo Institute of Technology. Previously, I was at Japan Advanced Institute of Science and Technology. I completed my Ph.D. at Tokyo Institute of Technology in 2018.
Email: thiem at artic.iir.titech.ac.jp
Research Interests
My research interests lie at the intersection of computer architecture, reconfigurable computing, and machine learning.
Research Grants
Principal Investigator / 研究代表者
Grant-in-Aid for Scientific Research (B) / 科研費 基盤研究(B)
研究課題名: 自己適応型エッジAIオンライン学習基盤の創出
研究期間: Apr 2024 - Mar 2029
総額: 18,720千円
Grant-in-Aid for Early-Career Scientists / 科研費 若手研究
研究課題名: 大規模疎行列処理のためのインストレージアクセラレータの創出
研究期間: Apr 2021 - Mar 2024
総額: 4,680千円
Grant-in-Aid for JSPS Fellows / 科研費 特別研究員奨励費
研究課題名: FPGAを用いた正確で高速なメニーコアエミュレーション
研究期間: Apr 2017 - Mar 2019
総額: 1,700千円
Co-Investigator / 研究分担者
Grant-in-Aid for Scientific Research (S) / 科研費 基盤研究(S)
研究代表者氏名: 本村 真人
研究課題名: 超高次元分散ベクトル表現を基軸とする融合型AIコンピューティング基盤の開拓
研究期間: Apr 2023 - Mar 2028
総額: 204,100千円
分担額(見込): 約20,000千円
NEDO／高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発／研究開発課題発掘のための先導調査研究
研究代表者氏名: 吉瀬 謙二
研究課題名: FPGAを活用するAI-IoTシステムの開発基盤に関する調査研究
研究期間: Aug 2021 - Jun 2022
総額: 100,000千円
分担額: 970千円
Research Collaborator / 研究協力者
JST Strategic Basic Research Programs (CREST) / JST戦略的創造研究推進事業 (CREST)
研究代表者氏名: 本村 真人
研究領域: Society 5.0を支える革新的コンピューティング技術
研究課題名: 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用
協力期間: Apr 2020 - Mar 2024
Joint Research with Companies / 民間企業との共同研究
Awards
Best Paper Award, The 20th IEEE International Conference on Field-Programmable Technology (FPT 2021)
Best Paper Award, The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017)
JSPS Research Fellowships for Young Scientists
学生奨励賞，情報処理学会 第77回全国大会
Awards of Students / 指導学生の受賞
Yuta Nagahara, 東京工業大学 工学院 情報通信系 優秀学生賞（修士） (Mar 2024)
Yuta Nagahara, Excellent Student Author Award for ASP-DAC 2024 (Feb 2024)
Publications
2024
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
The Genetic and Evolutionary Computation Conference (GECCO), Jul 2024ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data
Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
International Joint Conference on Neural Networks (IJCNN), Jun 2024Restricted Random Pruning at Initialization for High Compression Range
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
Transactions on Machine Learning Research (TMLR), May 2024Efficient Deadlock Avoidance for 2D Mesh NoCs that Use OQ or VOQ Routers
Philippos Papaphilippou, Thiem Van Chu
IEEE Transactions on Computers (TC), May 2024Progressive Variable Precision DNN with Bitwise Ternary Accumulation
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Artificial Intelligence Circuits and Systems (AICAS), Apr 2024Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Mar 2024Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2024Toward Improving Ensemble-Based Collaborative Inference at the Edge
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
IEEE Access, Jan 2024Pianissimo: A Sub-mW Class DNN Accelerator with Progressively Adjustable Bit-Precision
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
IEEE Access, Jan 2024Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
International Conference on Consumer Electronics (ICCE), Jan 2024An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection
Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024High Throughput Datapath Design for Vision Permutator FPGA Accelerator
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024
2023
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec 2023A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
IEICE Transactions on Information and Systems, Dec 2023Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Learning on Graphs Conference (LoG), Nov 2023Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Symposium on VLSI Technology and Circuits (VLSI), Jun 2023Decision Forest Training Accelerator Based on Binary Feature Decomposition
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2023 (Poster)Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), Apr 2023Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
International Solid-State Circuits Conference (ISSCC), Feb 2023An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration
Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu
IEEE Access, Jan 2023
2022
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
IEICE Transactions on Information and Systems, Dec 2022Multicoated Supermasks Enhance Hidden Networks
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Conference on Machine Learning (ICML), Jul 2022APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Jun 2022Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
International Solid-State Circuits Conference (ISSCC), Feb 2022
2021
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Conference on Field-Programmable Technology (FPT), Dec 2021
Best Paper AwardEdge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Hot Chips, Aug 2021 (Poster)ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Journal of Networking and Computing (IJNC), Jul 2021ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Journal of Networking and Computing (IJNC), Jul 2021
2020
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Symposium on Computing and Networking (CANDAR), Nov 2020ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Symposium on Computing and Networking (CANDAR), Nov 2020Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka
International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2020
2019
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes
Thiem Van Chu, Kenji Kise
IEICE Transactions on Information and Systems, Dec 2019
2018
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs
Thiem Van Chu, Kenji Kise
International Conference on Field-Programmable Logic and Applications (FPL), Aug 2018A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath
Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise
International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr 2018
2017
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
Thiem Van Chu, Shimpei Sato, Kenji Kise
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Dec 2017Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip
Thiem Van Chu, Myeonggu Kang, Shi FA, Kenji Kise
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2017High-Performance Hardware Merge Sorter
Susumu Mashimo, Thiem Van Chu, Kenji Kise
International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2017
Best Paper AwardCost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator
Susumu Mashimo, Thiem Van Chu, Kenji Kise
ACM SIGARCH Computer Architecture News - HEART'16, Jan 2017
2016
A Cost-effective and Scalable Merge Sorter Tree on FPGAs
Takuma Usui, Thiem Van Chu, Kenji Kise
International Symposium on Computing and Networking (CANDAR), Nov 2016The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
International Symposium on Networks-on-Chip (NOCS), Sep 2016
2015
Ultra-Fast NoC Emulation on a Single FPGA
Thiem Van Chu, Shimpei Sato, Kenji Kise
International Conference on Field-Programmable Logic and Applications (FPL), Sep 2015Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a single FPGA
Thiem Van Chu, Shimpei Sato, Kenji Kise
International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2015 (Short Paper)
2014
KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs
Thiem Van Chu, Shimpei Sato, Kenji Kise
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2014Ultrasmall: The Smallest MIPS Soft Processor
Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise
International Conference on Field Programmable Logic and Applications (FPL), Sep 2014 (Poster)