DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, xxx 2025
BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
Jiale Yan, Hiroaki Ito, Yuta Nagahara, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
International Symposium on Computer Architecture (ISCA), Jun 2025
Retraining Gradient Boosting Decision Trees with Backward Compatibility of Explanations
Tsukasa Yamakura, Yoichi Sasaki, Yuzuru Okajima, Thiem Van Chu
Pacific-Asia Conference on Knowledge Discovery and Data Mining (PAKDD), Jun 2025
TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding
Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), Apr 2025
Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning
Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
Transactions on Machine Learning Research (TMLR), Mar 2025
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
Transactions on Machine Learning Research (TMLR), Feb 2025
A Flip-count-based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms Date of Evaluation
Genta Inoue, Daiki Okonogi, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
IEICE Transactions on Information and Systems, Jan 2025
A Parallel-trial Double-update Annealing Processor for Enabling Highly-effective Solution Search of Constrained Combinatorial Optimization Problems
Akira Hyodo, Satoru Jimbo, Daiki Okonogi, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
International Conference on Field-Programmable Technology (FPT), Dec 2024
Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
International Symposium on Computing and Networking (CANDAR), Nov 2024
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura
Asian Solid-State Circuits Conference (A-SSCC), Nov 2024
Efficient Stereo Visual Odometry on FPGA featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
IEEE Access, Sep 2024
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
The Genetic and Evolutionary Computation Conference (GECCO), Jul 2024
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data
Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
International Joint Conference on Neural Networks (IJCNN), Jun 2024
Restricted Random Pruning at Initialization for High Compression Range
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
Transactions on Machine Learning Research (TMLR), May 2024
Efficient Deadlock Avoidance for 2D Mesh NoCs that Use OQ or VOQ Routers
Philippos Papaphilippou, Thiem Van Chu
IEEE Transactions on Computers (TC), May 2024
Progressive Variable Precision DNN with Bitwise Ternary Accumulation
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Artificial Intelligence Circuits and Systems (AICAS), Apr 2024
Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Mar 2024
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2024
Toward Improving Ensemble-Based Collaborative Inference at the Edge
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
IEEE Access, Jan 2024
Pianissimo: A Sub-mW Class DNN Accelerator with Progressively Adjustable Bit-Precision
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
IEEE Access, Jan 2024
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
International Conference on Consumer Electronics (ICCE), Jan 2024
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection
Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024
High Throughput Datapath Design for Vision Permutator FPGA Accelerator
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Conference on Consumer Electronics (ICCE), Jan 2024
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec 2023
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
IEICE Transactions on Information and Systems, Dec 2023
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Learning on Graphs Conference (LoG), Nov 2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Symposium on VLSI Technology and Circuits (VLSI), Jun 2023
Decision Forest Training Accelerator Based on Binary Feature Decomposition
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2023 (Poster)
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), Apr 2023
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
International Solid-State Circuits Conference (ISSCC), Feb 2023
An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration
Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu
IEEE Access, Jan 2023
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
IEICE Transactions on Information and Systems, Dec 2022
Multicoated Supermasks Enhance Hidden Networks
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Conference on Machine Learning (ICML), Jul 2022
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Jun 2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
International Solid-State Circuits Conference (ISSCC), Feb 2022