My primary research interests are power aware design of Network on Chip and System on Chip. I am also looking into design challenges of nano scale CMOS architectures from Power Management perspective. I am a research assistant at Embedded Systems & Co-Design Lab at Texas A&M University. I am working with Dr. Rabi Mahapatra.
Low Power Network on Chip Architectures
Network on Chip components account for a large fraction of the chip power consumption. This project deals with NoC power management issues. We apply non deterministic algorithms to control power consumption in various NoC components. Some of the techniques are hotspot avoidance routing, multilevel throttling and biologically inspired approaches. My work in low power NoC architecture can be laid out in the following areas:
System Level Power Management: Algorithm, Techniques and Approaches for low power operation of NoC. I have developped an Ant System based distributed power management technique to work at system level. This scheme distributes the power budget adaptively to the areas of the SoC based on demand while keeping the communication overhead to a minimum.
Low Power NoC Component Architecture: I am in the process of developing low power architectures for NoC router. Since routers are the most prominent component in the NoC infrastructure. I am investigating the effects of nanoscale CMOS elements in the overall power consumption scenario and developing low power architecture that is optimized for the future nanoscale design techniques.
Dynamic Flow State Management for low power network on chip. I am investigating methods to lower power consumption by dynamically scaling available bandwidth along with DVFS techniques.
NoCSim 2 and NoCBench
NoCSim 2 is a Network on Chip simulator designed using SystemC 2.0. It is designed at different abstraction level to serve various needs for accuracy and speed. The simulator is driven by an easy XML configuration and supports any topology and network size. The Simulator library has a collection of pre-designed network component with standard design principles for quick system implementation and testing. A public release of the simulator package will be available soon. NoCBench is an extension of NoCSim that also supports full system simulation with benchmark applications tweaked to evaluate Network on Chip designs. [Slides] [Details]
Security in Network on Chip based System on Chip
With ever increasing number of cores in today's SoC, security is becoming matter of concern. In a many core SoC, security issue can arise from a malicious code running in one of the cores possibly with privileged execution level. We are looking into biological immune system inspired approach towards autonomous security framework in System on Chips. In this research, specifically using the Network on Chip as a secure infrastructure, we mimic the functionality of biological immune system agents. The initial work has been published in SAW-I. [Details]
Low Power Hardware Scheduler for Real Time Multiprocessor System on Chip
Due to the increasing power consumption in systems, power management techniques are very common in todays designs. However, it has been shown that aggresive power management can severely harm a system's reliability. We have proposed techniques to manage reliability and power management in an integrated fashion so that system reliability is preserved while minimizing energy consumption. We are researching novel scheduling algorithm for both uniprocessor and multiprocessor systems employing these techniques.
IntellBatt: A Smarter Battery
IntellBatt is an intelligent approach towards smart battery design for wireless mobile systems. IntellBatt employs a low power onboard controller to schedule the operation of the cell array in the battery to extract the most out of them. Experiments have demonstrated upto 20% improvement in the battery discharge cycle length usign the system.
Power-aware Control of Environmental Sensor Network
This project was a part of SensorScope II, a swiss research and technology project initiated by NCCR-MICS in EPFL, Switzerland. I have worked on this project as a research intern. The aim of the project is to develop a robust sensor network system to monitor the environment. I worked on data analysis and power aware control algorithm development. Upon completion of this work the SensorScope II will evolve into SensorScope III which is the next generation of the system. A better perspective on the system can be obtained on the SensorScope Homepage. [Full Report]
Minimizing Channel Switching Delay by Intelligent Prefetch in IPTV Systems
This project proposes a method to intelligently prefetch the most used channels to avoid unexpected delay while switching channels in a IPTV System. [Report]
S. K. Mandal and R. N. Mahapatra, "PowerAntz: Ant behavior inspired power budget distribution scheme for Network on Chip systems", to appear in Microelectronics Journal.
S. K. Mandal, R. Denton, S. P. Mohanty and R. Mahapatra, "Low Power Nanoscale Buffer Management for Network on Chip Routers", To appear in Proceedings of GLSVLSI 2010.
S. K. Mandal, R. Mahapatra, P. Bhojwani and S. P. Mohanty, "IntellBatt: A Smarter Battery", IEEE Computer vol 42 issue. 3, March 2010, pp. 67-71.
A. Mandal, S. K. Mandal, A. Tripathy, N. Gupta and R. Mahapatra, "A Bio-Inspired Framework for Secure System on Chip", Workshop on SoC Architecture, Accelerators and Workloads, 2010. [Paper]
N. Gupta, S. K. Mandal, A. Mandal, J. Malave and R. Mahapatra, "A Hardware Scheduler for Real Time Multiprocessor System on Chip", To Appear in International Conference on VLSI Design, 2010.
S. K. Mandal, N. Gupta, A. Mandal, J. Malave, J. D. Lee and R. Mahapatra, "NoCBench: A Benchmarking Platform for Network-on-Chip", In Proceedings of Workshop on Unique Chips and Systems, 2009
S. K. Mandal, P. Bhojwani, S. Mohanty, R. Mahapatra, "IntellBatt: Towards Smarter Battery Design", Proceedings of ACM/IEEE Design Automation Conference, 2008 [PDF]
S. K. Mandal, R. N. Mahapatra, "PowerAntz: Distributed Power Sharing Strategy for Network on Chip”, Proceedings of International Symposium on Low Power Electronic Design, 2008 [PDF]
S. K. Mandal, C. Cianci, "Power Aware Control of an Environmental Sensor Network", Project Summary, SWIS, EPFL Switzerland, 2007 [PDF]
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