Shimpei Sato, Ph.D.

Affiliation
Assistant Professor
Department of Information and Communications Engineering
School of Engineering
Tokyo Institute of Technology

Contact
satos [at] ict.e.titech.ac.jp

Short Biography
  • April 2016 to present, Assistant Professor at Tokyo Tech, Japan
  • April 2015 to March 2016, Postdoctoral Researcher at Tokyo Tech, Japan
  • Octber 2014 to March 2015, Postdoctoral Researcher at JAIST, Japan
  • Received D.E. from Tokyo Institute of Technology in 2014
  • April 2010 to March 2012, JSPS research fellow (DC2)
  • Received M.E. from Tokyo Institute of Technology in 2009
  • Received B.E. from Tokyo Institute of Technology in 2007
Research Interests
  • Digital Circuit Design
  • High Performance Computing
    • Performance analysis, Performance tuning
  • Computer Architecture
    • Software simulator, Many-core processor, Network on Chip
  • FPGA
    • Soft processor, Hardware emulation
  • Hardware Description Language
    • RTL simulation
Publications
Journal papers
    1. Thiem Van Chu, Shimpei Sato, and Kenji Kise,
      Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA,
      ACM Transactions on on Reconfigurable Technology and Systems. (to appear)
    2. Shimpei Sato, Naoki Fujieda, Akira Moriya, and Kenji Kise,
      SimCell: A Processor Simulator for Multi-Core Architecture Research
      ,
      IPSJ Transactions on Advanced Computing Systems, Vol. 2, No. 1, pp. 146-157, March 2009. (IPSJ Digital Courier Funai Young Researcher Encouragement Award)
Conference papers
  1. Hiroki Nakahara, Tomoya Fujii, and Shimpei Sato,
    A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA,
    In Proceedings of the 27th International Conference on Field-programmable Logic and Applications (FPL '17) (short paper), pp. xx-xx, September 2017.
  2. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, and Shimpei Sato,
    GUINNESS: A GUI based neural network synthesizer for an FPGA,
    The 27th International Conference on Field-programmable Logic and Applications (FPL '17) (Demo), 
    September 2017.
  3. Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, and Masato Motomura,
    In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks,
    In Proceedings of the 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '17), August 2017.( to appear)
  4. Kano Akagi, Shimpei Sato, and Atsushi Takahashi,
    An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing,
    In Proceedings of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017), July 2017.
  5. Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, and Masato Motomura,
    BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator in 65 nm CMOS,
    The 2017 Symposia on VLSI Technology and Circuits, June 2017.
  6. Hiroki Nakahara, Akira Jinguji, Simpei Sato, and Tsutomu Sasao,
    A Random Forest using a Multi-valued Decision Diagram on an FPGA,
    In Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic (ISMVL '17), May 2017.
  7. Tomoya Fujii, Shimpei Sato, Hiroki Nakahara, and Masato Motomura,
    An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning,
    In Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC '17), pp. 268-280, April 2017.
  8. Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, and Shimpei Sato,
    An Acceleration of a Random Forest Classification using Altera SDK for OpenCL,
    The International Conference on Field-Programmable Technology (FPT '16), pp. 285-288, December 2016. (Poster)
  9. Shimpei Sato, Hiroshi Nakatsuka, and Atsushi Takahashi,
    Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection,
    The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), pp. 60-65, October 2016.
  10. Kurose Takahisa, Hiroki Nakahara, Shimpei Sato, and Tetsuo Morimoto,
    A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture,
    The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), pp. 280-281, October 2016.
  11. Shimpei Sato, Yukinori Sato, and Toshio Endo,
    A Cache-aware Temporal Blocking Method for 3D Stencil Computation,
    The 3rd
    International Workshop on High-Performance Stencil Computations (HiStencils 2016), January 2016. (Held in conjunction with HiPEAC)
  12. Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, and Kenji Kise,
    Effective Parallel Simulation of ArchHDL under Manycore Environment,
    In Proceedings of the 3rd International Symposium on Computing and Networking -Across Practical Development and Theoretical Research- (CANDAR '15), December 2015.
  13. Shimpei Sato, Yukinori Sato, and Toshio Endo,
    Investigating Potential Performance Benefits of Memory Layout Optimization based on Roofline Model,
    The 2nd Workshop on Software Engineering for Parallel Systems (SEPS 2015), October 2015. (Held in conjunction with SPLASH)
  14. Yukinori Sato, Shimpei Sato, and Toshio Endo,
    Exana: An Execution-driven Application Analysis Tool for Assisting Productive Performance Tuning,
    The 2nd Workshop on Software Engineering for Parallel Systems (SEPS 2015), October 2015. (Held in conjunction with SPLASH)
  15. Thiem Van Chu, Shimpei Sato, and Kenji Kise,
    Ultra-Fast NoC Emulation on a Single FPGA,
    In Proceedings of the 25th International Conference on Field-programmable Logic and Applications (FPL '15), September 2015.
  16. Thiem Van Chu, Shimpei Sato, and Kenji Kise,
    Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA,
    In Proceedings of the 22nd International S
    ymposium on Field-Programmable Custom Computing Machines (FCCM '15)(short paper), May 2015.
  17. Shimpei Sato, and Kenji Kise,
    ArchHDL: A Novel Hardware RTL Development Environment in C++,
    In Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC '15), April 2015.
  18. Thiem Van Chu, Shimpei Sato, and Kenji Kise,
    KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs,
    In Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '14), 
    pp. 215-222, September 2014.
  19. Shimpei Sato, and Kenji Kise,
    ArchHDL: A New Hardware Description Language for High-Speed Architectural Evaluation,
    In Proceedings of the IEEE 7th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '13), pp. 107-112, September 2013.
  20. Yuichiro Tanaka, Shimpei Sato, and Kenji Kise,
    The Ultrasmall Soft Processor,
    In Proceedings of the 4th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART '13), pp. 63-68, June 2013.
  21. Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato, and Kenji Kise,
    Request Density Aware Fair Memory Scheduling,
    The 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC), June 2012. (Held  in conjunction with ISCA)
    (Performance Track Award)
  22. Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise,
    SmartCore System for Dependable Many-core Processor with Multifunction Routers,
    In Proceedings of the 1st International Conference on Networking and Computing (ICNC '10), pp. 133-139, November 2010.
  23. Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise,
    Pattern-based Systematic Task Mapping for Many-core Processors,
    The 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS '10), pp. 173-178, November 2010. (H
    eld in conjunction with ICNC)
  24. Koh Uehara, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise,
    A Study of an Infrastructure for Research and Development of Many-Core Processors,
    In Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT '09), pp. 414-419, December 2009.
  25. Shimpei Sato, Naoki Fujieda, Akira Moriya, and Kenji Kise,
    Processor Simulator SimCell to Accelerate Research on Many-core Processor Architectures,
    The Workshop on Cell Systems and Applications (WCSA), pp. 119-127, June 2008. (Held in conjunction with ISCA)

Invited Talks
  1. Shimpei Sato,
    A Digital Circuit Design for Approximate Computing,
    The 26th International Workshop on Post-Binary ULSI Systems (ULSIWS2017), May 2017.
               
Posters and Etc
  1. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, and Shimpei Sato,
    On a Binarized / Ternarized Deep Neural Network Toward FPGA Realization,
    The 26th International Workshop on Post-Binary ULSI Systems (ULSIWS2017), May 2017.
  2. Shimpei Sato,
    Design Method for High-speed Digital Circuits with Speculative Execution,
    Japan-Taiwan International Engineering Forum 2017, March 2017.
  3. Shimpei Sato, Akihiko Saijo, and Yukinori Sato,
    A Profiling Tool set for measuring B/F Ratios and Cache Behaviors from Actual Applications,
    Poster session at JST/CREST International Symposium on Post Petascale System Software (ISP2S2), December 2014.
  4. Shimpei Sato, Akihiko Saijo, and Yukinori Sato,
    Profiling B/F Ratios and Cache Behaviors within Loop and Call Nests in the Actual Program Execution,
    Poster session at 2014 ATIP Workshop on Japanese Research Toward Next-Generation Extreme Compuring, November 2014. (Held in conjunction with SC)[site]
  5. Shimpei Sato, Yuki Matsubara, Akihiko Saijo, and Yukinori Sato,
    An Application Profiling Toolchain for Accelerating Systems with Deeper Memory Hierarchy,
    JAIST Booth Exhibit at the 2014
     International Conference for High Performance Computing, Networking, Storage, and Analysis (SC '14), November 2014.
  6. Shimpei Sato and Kenji Kise,
    Ultra-High Speed Architectural Simulation Methodology,
    The 16th
     International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA '14), March 2014.
  7. Shimpei Sato, Shinya Takamaeda, and Kenji Kise,
    DMR mode of SmartCore system,
    Poster session at the 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC '10), December 2010.
  8. Shinya Takamaeda, Shimpei Watanabe, Shimpei Sato, Koh Uehara, Yuhta Wakasugi, Naoki Fujieda, Yosuke Mori, and Kenji Kise,
    ScalableCore : High-Speed Prototyping System for Many-Core Processors,
    Poster session at the 12th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XII), p. 161, April 2009.
Awards
    1. IPSJ SIGARC Young Researcher Award, 2014.
    2. Performance Track Award, the 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC), 2012.
    3. Most Interesting Poster Award, IPSJ Symposium on Advanced Computing Systems and Infrastructures (SACSIS), 2010.
    4. IPSJ Digital Courier Funai Young Researcher Encouragement Award, 2010.
    5. Poster Award, IPSJ Computer System Symposium (ComSys), 2008.
    6. IEICE Tokyo Section Student Award, 2008.
Academic Service
  • Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Secretary, 2017, 2018.
  • International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Program Committee Member, 2017.
  • International Symposium on Computing and Networking (CANDAR), Program Committee Member, 2017.
  • International Workshop on Advances in Networking and Computing (WANC), Program Committee Member, 2016, 2017.