Shimpei Sato, Ph.D.

Affiliation

Associate Professor

Department of Electrical and Computer Engineering, Faculty of Engineering, Shinshu University

Contact

satos [at] shinshu-u.ac.jp

Short Biography

• March 2023 to presetn, Associate Professor at Shinshu University, Japan

• April 2021 to February 2023, Assistant Professor at Shinshu University, Japan

• April 2016 to March 2021, Assistant Professor at Tokyo Tech, Japan

• April 2015 to March 2016, Postdoctoral Researcher at Tokyo Tech, Japan

• October 2014 to March 2015, Postdoctoral Researcher at JAIST, Japan

• Received D.E. from Tokyo Institute of Technology in 2014

• April 2010 to March 2012, JSPS research fellow (DC2)

• Received M.E. from Tokyo Institute of Technology in 2009

• Received B.E. from Tokyo Institute of Technology in 2007

Research Interests

• Digital Circuit Design

• High Performance Computing

  • Performance analysis, Performance tuning

• Computer Architecture

  • Software simulator, Many-core processor, Network on Chip

• FPGA

  • Soft processor, Hardware emulation

• Hardware Description Language

  • RTL simulation

Publications

Journal papers

• [J18] Akira Jinguji, Shimpei Sato and Hiroki Nakahara, "Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs", IEICE TRANSACTIONS on Information and Systems, Vol. E104-D, No. 12, pp. 2040-2047, December 2021.

• [J17] Hiroyoshi Tanabe, Shimpei Sato and Atsushi Takahashi, "Fast EUV lithography simulation using convolutional neural network," Journal of Micro/Nanopatterning, Materials and Metrology (JM3). 20(4), 041202, pp. 1-13, September 2021. 

• [J16] Naoto Soga, Shimpei Sato and Hiroki Nakahara, "Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder," IEICE TRANSACTIONS on Information and Systems, Vol. E104-D, No.8, pp. 1121-1129, August 2021.

• [J15] Yuta Ukon, Shimpei Sato and Atsushi Takahashi, "Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism," IEICE TRANSACTIONS on Electronics, Vol. E104-C, No. 7, pp. 309-318, July 2021.

• [J14] Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato and Hiroki Nakahara, "SENTEI: Filter-wise Pruning with Distillation Towards Efficient Sparse Convolutional Neural Network Accelerators," IEICE TRANSACTIONS on Information and Systems, Vol. E103-D, No.12, pp. 2463-2470, December 2020.

• [J13] Shimpei Sato, Kano Akagi and Atsushi Takahashi, "A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem using Selective Pin-Pair Connections", IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E103-A, No. 09, pp. 1037-1044, September 2020.

• [J12] Shimpei Sato, Eijiro Sassa, Yuta Ukon and Atsushi Takahashi, "A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution," IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E102-A, No. 12, pp. 1760-1769, December 2019.

• [J11] Masayuki Shimoda, Shimpei Sato and Hiroki Nakahara, "Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA, IEICE TRANSACTIONS on Information and Systems," Vol. E102-D, No. 5, pp. 1020-1028, May 2019.

• [J10] Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda and Shimpei Sato," GUINNESS: A GUI based Binarized Deep Neural Network Framework for Software Programmers," IEICE TRANSACTIONS on Information and Systems, Vol. E102-D, No. 5, pp. 1003-1011, May 2019.

• [J9] Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda and Masato Motomura, "BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W," IEEE Journal of Solid-State Circuits, Vol. 53, Issue 4, pp. 983-994, April 2018.

• [J8] Shimpei Sato, Ryohei Kobayashi and Kenji Kise, "ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment," IEICE TRANSACTIONS on Information and Systems, Vol. E101-D, No. 2, pp. 344-353, February 2018.

• [J7] Akira Jinguji, Shimpei Sato and Hiroki Nakahara, "An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design," IEICE TRANSACTIONS on Information and Systems, Vol. E101-D, No. 2, pp. 354-362, February 2018.

• [J6] Tomoya Fujii, Shimpei Sato and Hiroki Nakahara, "A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA," IEICE TRANSACTIONS on Information and Systems, Vol. E101-D, No. 2, pp. 376-386, February 2018.

• [J5] Thiem Van Chu, Shimpei Sato and Kenji Kise, "Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA," ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 10, Issue 4, pp. 27:1-27:27, December 2017.

• [J4] Shimpei Sato and Kenji Kise, "Pipeline Bypassing Method for Distributed Shared-Buffer NoC Router," IPSJ Transactions on Advanced Computing Systems, Vol. 5, No. 1, pp. 88-102, January 2012. (in Japanese)

• [J3] Shinya Takamaeda，Shimpei Sato, Naoki Fujieda, Takefumi Miyoshi and Kenji Kise, "ScalableCore System: Hardware Environment for Many-core Architectures Evaluation," IPSJ Transactions on Advanced Computing Systems, Vol. 4, No. 1, pp. 24-42, February 2011. (in Japanese)

• [J2] Koh Uehara, Shimpei Sato and Kenji Kise, "A Practical Infrastructure for Researches and Education of Many-Core Processors," IEICE TRANSACTIONS on Information and Systems, Vol. J93-D, No. 10, pp. 2042-2057, October 2010. (in Japanese)

• [J1] Shimpei Sato, Naoki Fujieda, Akira Moriya and Kenji Kise, "SimCell: A Processor Simulator for Multi-Core Architecture Research," IPSJ Transactions on Advanced Computing Systems, Vol. 2, No. 1, pp. 146-157, March 2009. (IPSJ Digital Courier Funai Young Researcher Encouragement Award)

Conference papers

• [C52] Tahsin Shameem, Shimpei Sato, Atsushi Takahashi, Hiroyoshi Tanabe, Yukihide Kohira and Chikaaki Kodama, "A Fast LUT Based Point Intensity Computation for OPC Algorithm," in Proceedings of the 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021), pp. 92-97, March 2021. (to appear)

• [C51] Hiroyoshi Tanabe, Shimpei Sato and Atsushi Takahashi, “Fast 3D lithography simulation by convolutional neural network,” SPIE Proceedings, Vol. 11614, Design-Process-Technology Co-optimization XV, pp. 116140M-1-116140M-8, February 2021.

• [C50] Yuta Suzuki, Naoto Soga, Shimpei Sato and Hiroki Nakahara, "A Table Look-Up Based Ternary Neural Network Processor," in Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic (ISMVL '20), pp. 188-193, November 2020.

• [C49] Hiroyoshi Tanabe, Shimpei Sato and Atsushi Takahashi, "Fast 3D lithography simulation by convolutional neural network: POC study," in Proceedings of SPIE Vol. 11518, Photomask Technology 2020, pp. 91-97, September 2020.

• [C48] Akira Jinguji, Shimpei Sato and Hiroki Nakahara, "Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs," in Proceedings of the 28th International Symposium on Field-Programmable Custom Computing Machines (FCCM '20), p. 229 May 2020.

• [C47] Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato and Hiroki Nakahara, "Fast Monocular Depth Estimation on an FPGA," in Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW '20), pp. 143-146, May 2020. (RAW '20)

• [C46] Hidekazu Takahashi, Hiroki Ogura, Shimpei Sato, Atsushi Takahashi and Chikaaki Kodama, "A feature selection method for weak classifier based hotspot detection," in Proceedings of SPIE Vol. 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, pp. 310-316, March 2020.

• [C45] Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato and Hiroki Nakahara, "FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System," in Proceedings of the 2019 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019), pp. 1-5, December 2019.

• [C44] Hidekazu Takahashi, Shimpei Sato and Atsushi Takahashi, "A Fast Hotspot Detector Based on Local Features Using Concentric Circle Area Sampling," in Proceedings of the 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019), pp. 316-321, October 2019.

• [C43] Naoto Soga, Shimpei Sato and Hiroki Nakahara, "Energy-efficient ECG Signals Outlier Detection Hardware using a Sparse Robust Deep Autoencoder," in Proceedings of the 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019), pp. 2-7, October 2019. (Best Paper Award)

• [C42] Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato and Hiroki Nakahara, "Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks," in Proceedings of the IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '19), pp. 93-100, October 2019. (Best-paper Award Runner-up)

• [C41] Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji and Shimpei Sato, "FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network," in Proceedings of the 28th International Conference on Field-programmable Logic and Applications (FPL '19), pp. 180-186, September 2019.

• [C40] Shimpei Sato, Eijiro Sassa, Yuta Ukon and Atsushi Takahashi, "A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution," in Proceedings of the 2019 IEEE International Symposium on Circuits and Systems (ISCAS '19), pp. 1-5, May 2019.

• [C39] Atsuki Munakata, Hiroki Nakahara and Shimpei Sato, "Noise Convolutional Neural Networks and FPGA Implementation," in Proceedings of the 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL '19), pp. 85-90, May 2019.

• [C38] Hiroki Nakahara, Masayuki Shimoda and Shimpei Sato, "A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector," in Proceedings of the International Conference on Field-Programmable Technology (FPT '18), pp. 298-301, December 2018.

• [C37] Akira Jinguji, Tomoya Fujii, Shimpei Sato and Hiroki Nakahara, "An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network," in Proceedings of the International Conference on Field-Programmable Technology (FPT '18), pp. 310-313, December 2018.

• [C36] Hiroki Nakahara, Masayuki Shimoda and Shimpei Sato, "A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)," in Proceedings of the 28th International Conference on Field-programmable Logic and Applications (FPL '18), pp. 457-458, August 2018.

• [C35] Masayuki Shimoda, Shimpei Sato and Hiroki Nakahara, "Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs," in Proceedings of the 28th International Conference on Field-programmable Logic and Applications (FPL '18), pp. 461-462, August 2018.

• [C34] Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung and Ting-Chi Wang, "Pattern Similarity Metrics for Layout Pattern Classification and their Validity Analysis by Lithographic Responses," in Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI '18), pp. 494-497, July 2018.

• [C33] Masayuki Shimoda, Shimpei Sato and Hiroki Nakahara, "Power Efficient Object Detector with an Event-Driven Camera on an FPGA," in Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART '18), pp. 10:1-10:6, June 2018.

• [C32] Haoxuan Cheng, Shimpei Sato and Hiroki Nakahara, "A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)," in Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART '18), pp. 20:1-20:4, June 2018.

• [C31] Haruyoshi Yonekawa, Shimpei Sato and Hiroki Nakahara, "A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor," in Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic (ISMVL '18), pp. 174-179, May 2018.

• [C30] Kano Akagi, Shimpei Sato and Atsushi Takahashi, "Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing," in Proceedings of the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018), pp. 337-342, March 2018.

• [C29] Tomoya Fujii, Shimpei Sato and Hiroki Nakahara, "A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolutional Neural Network on an FPGA," in Proceedings of the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018), pp. 308-313, March 2018.

• [C28] Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii and Shimpei Sato, "A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA," in Proceedings of the 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '18), pp. 31-40, February 2018.

• [C27] Hiroki Nakahara, Haruyoshi Yonekawa and Shimpei Sato, "An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA," in Proceedings of the International Conference on Field-Programmable Technology (FPT '17), pp. 168-175, December 2017.

• [C26] Masayuki Shimoda, Shimpei Sato and Hiroki Nakahara, "All Binarized Convolutional Neural Network and Its implementation on an FPGA," in Proceedings of the International Conference on Field-Programmable Technology (FPT '17), pp. 291-294, December 2017.

• [C25] Hiroki Nakahara, Tomoya Fujii and Shimpei Sato, "A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA," in Proceedings of the 27th International Conference on Field-programmable Logic and Applications (FPL '17), pp. 1-4, September 2017.

• [C24] Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda and Shimpei Sato, "A demonstraion of the GUINNESS: A GUI based neural network synthesizer for an FPGA," in Proceedings of the 27th International Conference on Field-programmable Logic and Applications (FPL '17), p. 1, September 2017.

• [C23] Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura, Haruyoshi Yonekawa, Shimpei Sato and Hiroki Nakahara, "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," in Proceedings of the 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '17), pp. 116-119, August 2017.

• [C22] Kano Akagi, Shimpei Sato and Atsushi Takahashi, "An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing," in Proceedings of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017), pp. 62-65, July 2017.

• [C21] Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda and Masato Motomura, "BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator in 65 nm CMOS," in Proceedings of the 2017 Symposia on VLSI Technology and Circuits (VLSI '17), pp. C24-C25,  June 2017.

• [C20] Hiroki Nakahara, Akira Jinguji, Shimpei Sato and Tsutomu Sasao, "A Random Forest using a Multi-valued Decision Diagram on an FPGA," in Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic (ISMVL '17), pp. 266-271, May 2017.

• [C19] Tomoya Fujii, Shimpei Sato, Hiroki Nakahara and Masato Motomura, "An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning," in Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC '17), pp. 268-280, April 2017.

• [C18] Hiroki Nakahara, Akira Jinguji, Tomoya Fujii and Shimpei Sato, "An Acceleration of a Random Forest Classification using Altera SDK for OpenCL," The International Conference on Field-Programmable Technology (FPT '16), pp. 285-288, December 2016.

• [C17] Shimpei Sato, Hiroshi Nakatsuka and Atsushi Takahashi, "Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection," in Proceedings of the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), pp. 60-65, October 2016.

• [C16] Takahisa Kurose, Hiroki Nakahara and Shimpei Sato, "Tetsuo Morimoto, A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture," in Proceedings of the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), pp. 280-281, October 2016.

• [C15] Shimpei Sato, Yukinori Sato and Toshio Endo, "A Cache-aware Temporal Blocking Method for 3D Stencil Computation," in Proceedings of the 3rd International Workshop on High-Performance Stencil Computations (HiStencils 2016), January 2016. (Held in conjunction with HiPEAC)

• [C14] Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato and Kenji Kise, "Effective Parallel Simulation of ArchHDL under Manycore Environment," in Proceedings of the 3rd International Symposium on Computing and Networking (CANDAR '15), pp. 140-146, December 2015.

• [C13] Shimpei Sato, Yukinori Sato and Toshio Endo, "Investigating Potential Performance Benefits of Memory Layout Optimization based on Roofline Model," in Proceedings of the 2nd Workshop on Software Engineering for Parallel Systems (SEPS 2015), pp. 50-56, October 2015. (Held in conjunction with SPLASH)

• [C12] Yukinori Sato, Shimpei Sato and Toshio Endo, "Exana: An Execution-driven Application Analysis Tool for Assisting Productive Performance Tuning," in Proceedings of the 2nd Workshop on Software Engineering for Parallel Systems (SEPS 2015), pp. 1-10, October 2015. (Held in conjunction with SPLASH)

• [C11] Thiem Van Chu, Shimpei Sato and Kenji Kise, "Ultra-Fast NoC Emulation on a Single FPGA," in Proceedings of the 25th International Conference on Field-programmable Logic and Applications (FPL '15), pp. 1-8, September 2015.

• [C10] Thiem Van Chu, Shimpei Sato and Kenji Kise, "Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA," in Proceedings of the 22nd International Symposium on Field-Programmable Custom Computing Machines (FCCM '15), pp. 60-63, May 2015.

• [C9] Shimpei Sato and Kenji Kise, "ArchHDL: A Novel Hardware RTL Development Environment in C++," in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC '15), pp. 53-64, April 2015.

• [C8] Thiem Van Chu, Shimpei Sato and Kenji Kise, "KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs," in Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '14), pp. 215-222, September 2014.

• [C7] Shimpei Sato and Kenji Kise, "ArchHDL: A New Hardware Description Language for High-Speed Architectural Evaluation," in Proceedings of the IEEE 7th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '13), pp. 107-112, September 2013.

• [C6] Yuichiro Tanaka, Shimpei Sato and Kenji Kise, "The Ultrasmall Soft Processor," in Proceedings of the 4th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART '13), pp. 63-68, June 2013.

• [C5] Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato and Kenji Kise, "Request Density Aware Fair Memory Scheduling," in Proceedings of the 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship, June 2012. (Held  in conjunction with ISCA) (Performance Track Award)

• [C4] Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi and Kenji Kise, "SmartCore System for Dependable Many-core Processor with Multifunction Routers," in Proceedings of the 1st International Conference on Networking and Computing (ICNC '10), pp. 133-139, November 2010.

• [C3] Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi and Kenji Kise, "Pattern-based Systematic Task Mapping for Many-core Processors," in Proceedings of the 1st International Conference on Networking and Computing (ICNC '10), pp. 173-178, November 2010.

• [C2] Koh Uehara, Shimpei Sato, Takefumi Miyoshi and Kenji Kise, "A Study of an Infrastructure for Research and Development of Many-Core Processors," in Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT '09), pp.414-419, December 2009.

• [C1] Shimpei Sato, Naoki Fujieda, Akira Moriya and Kenji Kise, "Processor Simulator SimCell to Accelerate Research on Many-core Processor Architectures," in Proceedings of the 2008 Workshop on Cell Systems and Applications (WCSA), pp. 119-127, June 2008. (Held in conjunction with ISCA)

Invited Talks

1. Shimpei Sato, "A Digital Circuit Design for Approximate Computing," The 26th International Workshop on Post-Binary ULSI Systems (ULSIWS2017), May 2017.

Posters and Etc

1. Atsushi Takahashi, Hidekazu Takahashi, Hiroki Ogura and Shimpei Sato, "Hotspot Detection Methods and their Evaluation in Advanced Lithography," in Proceedings of the 16th International SoC Design Conference (ISOCC '19), p. 121, October 2019.

2. Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda and Shimpei Sato, "An FPGA-based Fine Tuning Accelerator for a Sparse CNN," The 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '19), p. 186, February 2019.

3. Yusuke Kimura, Shimpei Sato and Atsushi Takahashi, "Flexible Two-Colorable Routing for Self-Aligned Double Patterning," The 2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS 2017), August 2017.

4. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii and Shimpei Sato, "On a Binarized / Ternarized Deep Neural Network Toward FPGA Realization," The 26th International Workshop on Post-Binary ULSI Systems (ULSIWS2017), May 2017.

5. Shimpei Sato, "A Design Method for High-speed Digital Circuits with Speculative Execution," Japan-Taiwan International Engineering Forum 2017, March 2017.

6. Shimpei Sato, Akihiko Saijo and Yukinori Sato, "A Profiling Tool set for measuring B/F Ratios and Cache Behaviors from Actual Applications," The JST/CREST International Symposium on Post Petascale System Software (ISP2S2), December 2014.

7. Shimpei Sato, Akihiko Saijo and Yukinori Sato, "Profiling B/F Ratios and Cache Behaviors within Loop and Call Nests in the Actual Program Execution," The 2014 ATIP Workshop on Japanese Research Toward Next-Generation Extreme Computing, November 2014. (Held in conjunction with SC)

8. Shimpei Sato, Yuki Matsubara, Akihiko Saijo and Yukinori Sato, "An Application Profiling Toolchain for Accelerating Systems with Deeper Memory Hierarchy," JAIST Booth Exhibit at the 2014 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC '14), November 2014.

9. Shimpei Sato and Kenji Kise, "Ultra-High Speed Architectural Simulation Methodology," The 16th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA '14), March 2014.

10. Shimpei Sato, Shinya Takamaeda and Kenji Kise, "DMR mode of SmartCore system," The 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC '10), December 2010.

11. Shinya Takamaeda, Shimpei Watanabe, Shimpei Sato, Koh Uehara, Yuhta Wakasugi, Naoki Fujieda, Yosuke Mori and Kenji Kise, "ScalableCore : High-Speed Prototyping System for Many-Core Processors," The 12th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XII), p. 161, April 2009.

Awards

1. Best Paper Award, The 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019), 2019.

2. Best-paper Award Runner-up,  The IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC '19), 2019.

3. IPSJ SIGARC Young Researcher Award, 2014.

4. Performance Track Award, the 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC), 2012.

5. Most Interesting Poster Award, IPSJ Symposium on Advanced Computing Systems and Infrastructures (SACSIS), 2010.

6. IPSJ Digital Courier Funai Young Researcher Encouragement Award, 2010.

7. Poster Award, IPSJ Computer System Symposium (ComSys), 2008.

8. IEICE Tokyo Section Student Award, 2008.

Academic Service

• Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Technical Program Committee Member, 2021.

• International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Program Committee Member, 2017, 2018.

• International Symposium on Computing and Networking (CANDAR), Program Committee Member, 2017 - cont.

• International Workshop on Advances in Networking and Computing (WANC), Program Committee Member, 2016 - 2018.

• IEEE CAS JJC, Treasurer, 2021 - cont.

• IEEE CEDA AJJC, Treasurer, 2019 - 2020.

• Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Secretary, 2017, 2018.