Project Scope

In this project we are looking at effective ways of parallelising the STA computation for digital integrated circuits. We would like to break the work into two steps Data representation and Computation as detailed below :

Step 1 : Input Data and representation

We aim to build an efficient database to store the the graph and data pertaining to the design.

The inputs for STA comprise of the following :

1) Verilog Netlist

This is the representation of the design , the standard cells , connectivity etc. The netlist might be visualized as a graph with the standard cells being the nodes and the nets being the edges. However later we see that once the parasitic information is read , additional nodes need to be created in the edges for distributed parasitics.

2) SPEF file (Parasitic Information)

This file represents contains information about the parasitics(resitance and capaitance) of every net in the design. the SPEF file may be of two types - Lumped and distributed. Lumped parasitics define a since capacitance and resistance value of each net in the design . Distributed parasitics break the nets into tiny elements and represents each of these elements by a PI network. Distributed parasitics also capture coupling between nets and can be used for crosstalk analysis.

3) SDC file (Design Constraints) :

This file represents the timing information of the design , such as clock sources and frequencies , input/output timing , "timing exceptions" ie. fake paths which will never get excited.

4) Standard cell liberty :

the synopsys liberty file format is a popular standard to represent the timing information of standard cells.

Step 2 : Timing computation

This step is the focus of this project , ie. computation of timing delays of paths and finding if the delay meets the spec. We plan to use the NVIDIA CUDA to hopefully parallelise the computation on the GPU.

As phase 1 of the project we aim to work with lumped parasitics . If we manage to get the lumped parasitics based STA working in time , we will try to do distributed parasitcs.