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Welcome to Sheng-Hong Wang's Website!

I am a Ph.D. candidate in the department of computer science and engineering at the University of California, Santa Cruz. My research interest is at the intersection of the Compiler designs for hardware description language and parallel programming. Before joining UCSC, I worked at Novatek as an advanced digital circuit designer for 5 years.

Currently, I am the student project leader of the LiveHD project under the supervision of Professor Jose Renau. LiveHD aims to build a fast and scalable hardware compiler for multi-HDLs. I am also developing the compiler stack of a modern hardware description language, Pyrope.

E-mail: swang203@ucsc.edu

News!

• • Nov. 2021: A Parallel HDL Compilation Framework accepted at WOSET'21!

  • Nov. 2021: A Guide for Rapid Creation of New HDLs accepted at WOSET'21!

  • Oct. 2021: I'm honored to have a talk for our parallelized LiveHD Framework at the Circt development meeting. Video.

  • Mar. 2021: Design Decisions in LiveHD accepted at LATTE'21!

  • May. 2020: I passed my advancement and became a Ph.D. candidate!

  • May. 2020: LiveHD accepted at IEEE-Micro!

  • May. 2020: I'm glad to have a talk about our LGraph and LNAST IR for productive hardware developments in UCSC Open-Source Hardware and EDA Seminar! (video link)

  • Apr. 2020: LiveSim accepted at ISPASS'20! (best paper nomination)

  • Sep. 2019: LGraph accepted at WOSET'19!

  • Sep. 2019: LNAST accepted at WOSET'19!

  • Sep. 2018: LGraph accepted at WOSET'18! (best tools nomination)