Publications

PUBLICATIONS

  1. A Parallel HDL Compilation Framework, Sheng-Hong Wang, Sakshi Garg, Hunter James Coffman, Kenneth Mayer, and Jose Renau, Fourth Workshop on Open-Source EDA Technology (WOSET), 2021.

  2. A Guide for Rapid Creation of New HDLs, SakshiGarg, Sheng-HongWang, HunterJamesCoffman, and Jose Renau, Fourth Workshop on Open-Source EDA Technology (WOSET), 2021.

  3. Design Decisions in LiveHD for HDLs Compilation, Sheng-Hong Wang and Jose Renau, 1st Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2021), April 2021.

  4. LiveHD: A Productive Live Hardware Development Flow, Sheng-Hong Wang, Rafael T. Possignolo, Haven Skinner, and Jose Renau, IEEE Micro Special Issue on Agile and Open-Source Hardware, 2020.

  5. LiveSim: A Fast Hot Reload Simulator for HDLs , Haven Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, and Jose Renau, International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020. (Best paper nomination)

6. LNAST: A Language Neutral Intermediate Representation for Hardware Description Languages, Sheng-Hong Wang, Akash Sridhar, and Jose Renau, Second Workshop on Open-Source EDA Technology (WOSET), 2019.

7. LGraph: A Unified Data Model and API for Productive Open-Source Hardware Design, Sheng-Hong Wang, Rafael T. Possignolo, Qian Chen, Rohan Ganpati, and Jose Renau, Second Workshop on Open-Source EDA Technology (WOSET), November 2019.

8. LGraph: A multi-language open-source database for VLSI, Rafael T. Possignolo, Sheng-Hong Wang, Haven Skinner, and Jose Renau. First Workshop on Open-Source EDA Technology (WOSET), November 2018.

9. New Methodology for Power Estimation in ASIC Early Stage - Siloti Power Estimation Flow, Sheng-Hong Wang, Tzung-Rung Jung, and Lance Liu. Synopsys Users Group Taiwan Conference 2015.

10. Fast Scalable Radix-4 Montgomery Modular Multiplier, Sheng-Hong Wang, Wen-Ching Lin, Jheng-Hao Ye, and Ming-Der Shieh. IEEE International Symposium on Circuits and Systems(ISCAS), pp. 3049-3052. IEEE, 2012.

11. Low-latency Scalable Dual-field Modular Multiplier Based on Radix-4 Montgomery Algorithm, Wen-Ching Lin, Sheng-Hong Wang, and Ming-Der Shieh. The 23rd VLSI Design/Cad Symposium, 2012.