Professional Experience

Deep Learning Computational Graph Engineer at Intel, San Diego, USA

July 2018 – present

1. Working at Habana, enabling and optimizing models for Gaudi, Goya and Gaudi2 (2020 - present)

   1. Developed a prototype onnxruntime backend for Goya, with features such as quantization

   2. Optimize models such as hubert, Segnet, LLaMA text generation, yolo, etc on different platforms such as hugging face and deep speed, deploying techniques such as dynamic-to-static conversion, padding/bucketing inputs, employing Gaudi media pipeline, Hpu graphs etc.

   3. Driving Dynamic shapes user experience:

      • Static compilation for HW poses challenges for dynamic inputs/ops. Authored documents, notebooks and evangelized to make users aware of these nuances, and provide strategies to detect and mitigate dynamicity of ops and inputs.

   4. Moderator of Habana Forum

2. Working at Nervana on the compiler front-end for Tensorflow to ngraph conversion (2018-2020)

   1. As a core contributor to the opensource nGraph Tensorflow bridge repo, involved in architectural design and implementation of the codebase, which allows one to convert Tensorflow deep learning models to nGraph, Intel's graph compiler.

      • Worked on features such as improvements to deadness analysis, ahead-of-time compilation, sub graph encapsulation, debug tools, model equivalance test framework, build systems.

   2. Enabled the running of multiple Tensorflow models using a deep understanding of graph algorithms, compiler theory, deep learning, C++ and Python

Intern (Autonomous Driving) at Nvidia Corporation, Santa Clara, USA

July 2012 – June 2014

1. Developed methods for estimating inference times of deep networks run using Tensor-RT on Drive-PX2

2. Developed testing and verification framework for integrating Tensorflow support in Tensor-RT

System Software Engineer at Nvidia Graphics Private Limited, Pune, India 

July 2012 – June 2014

1. As part of the Android Video Team, developed driver and microcode for hardware modules relating to video capture, playback and security in the Tegra mobile processor.

2. Designed and implemented a technique for dynamically scaling the frequency of the Video Decoder Engine in Tegra SoC, to reduce power consumption when playing videos, without dropping frames.

3. Worked on microcode of Tegra Security Engine (a cryptography module) for decrypting encrypted Transport Stream files, stripping the Packetized Elementary Header of the payload and then reencrypting the resulting Elementary Stream.

4. Developed parser, driver & microcode for the new codec VP9 (both normal & encrypted playback).

5. Automated unit testing and developed an interactive mixed mode disassembly tool for debugging microcode

Intern at Instruments Research and Development Establishment, Dehradun, India

May 2011 – June 2011

1. Developed drivers for interfacing ATmega2560 with OLED display screens, interfaced a PC and the ATmega2560 using an UART connection and implemented software debouncing of input buttons. Integrating above components, designed and implemented a menu driven user interface for operating systems like Laser Designators.

2. Received an ‘outstanding’ performance rating for contributions.