EQUIVALENT DEVICE STATISTICAL MODELING FOR BITLINE LEAKAGE MODELING
02/17/2009
Co-inventors: Joshi, R. KANJ, R. N.
MODEL-BASED RETARGETING OF LAYOUT PATTERNS FOR SUB-WAVELENGTH PHOTOLITHOGRAPHY
01/26/2009
Co-inventors: AGARWAL, K. B. BANERJEE, S.
GRADIENT-BASED SEARCH MECHANISM FOR OPTIMIZING PHOTOLITHOGRAPH MASKS
10/01/2008
Co-inventors: Liu, Y. SHI, X.
BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS
08/21/2008
Co-inventors: Joshi, R. KANJ, R. N. LI, Z.
COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION
07/07/2008
Co-inventors: AGARWAL, K. B. Acar, E. Jamsek, D.
INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA
07/07/2008
Co-inventors: AGARWAL, K. B. Acar, E. Jamsek, D.
A METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS
06/16/2008
Co-inventors: Joshi, R. KANJ, R. N.
ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT
04/21/2008
Co-inventors: Joshi, R. KANJ, R. N. Kuang, J.
BLENDED MODEL INTERPOLATION
03/12/2008
Co-inventors: Acar, E. Jamsek, D.
DELAY BASED BIAS TEMPERATURE INSTABILITY RECOVERY MEASUREMENTS FOR CHARACTERIZING STRESS DEGRADATION AND RECOVERY
09/27/2007
Co-inventors: Gebara, F. H. Hayes, J. D. Schaub, J. D.
METHOD AND COMPUTER PROGRAM FOR SELECTING CIRCUIT REPAIRS USING REDUNDANT ELEMENTS WITH CONSIDERATION OF AGING EFFECTS
08/27/2007
Co-inventors: Adams, C. Joshi, R. KANJ, R. N.
METHOD AND SYSTEM FOR DETERMINING ELEMENT VOLTAGE SELECTION CONTROL VALUES FOR A STORAGE DEVICE
08/27/2007
Co-inventors: Joshi, R. KANJ, R. N. Kuang, J. Ngo, H.
ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES
10/22/2007
Co-inventors: Joshi, R. KANJ, R. N. Kuang, J. Ngo, H.
METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES
10/22/2007
Co-inventors: Joshi, R. KANJ, R. N. Kuang, J. Ngo, H.
TECHNIQUES FOR PATTERN PROCESS TUNING AND DESIGN OPTIMIZATION FOR MAXIMIZING PROCESS-SENSITIVE CIRCUIT YIELDS
06/20/2007
Co-inventors: Chuang, C. Heng, F. KANJ, R. N. Kim, K. Lee, J. MUKHOPADHYAY, S. Singh, R. N.
CHARACTERIZATION CIRCUIT FOR FAST DETERMINATION OF DEVICE CAPACITANCE VARIATION
05/31/2007
Co-inventors: AGARWAL, K. B. Hayes, J. D.
METHOD AND TEST SYSTEM FOR FAST DETERMINATION OF PARAMETER VARIATION STATISTICS
06/20/2007
Co-inventors: AGARWAL, K. B. Hayes, J. D.
METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE
11/16/2006
Co-inventors: Braasch, S. C. Hibbeler, J. KANJ, R. N. Maynard, D. Papadopoulou, E.
CLOSED-LOOP MODELING OF GATE LEAKAGE FOR FAST SIMULATORS
10/02/2006
Co-inventors: Joshi, R. KANJ, R. N. Liu, Y. SIVAGNANAME, J.
METHOD AND CIRCUIT FOR MEASURING OPERATING AND LEAKAGE CURRENT OF INDIVIDUAL BLOCKS WITHIN AN ARRAY OF TEST CIRCUIT BLOCKS
09/13/2006
Co-inventors: ACHARYYA, D. RAO, R.
SCANNABLE VIRTUAL RAIL METHOD AND RING OSCILLATOR CIRCUIT FOR MEASURING VARIATIONS IN DEVICE CHARACTERISTICS
09/11/2006
Co-inventors: AGARWAL, K. B.
SCANNABLE VIRTUAL RAIL RING OSCILLATOR CIRCUIT AND SYSTEM FOR MEASURING VARIATIONS IN DEVICE CHARACTERISTICS
11/22/2006
Co-inventors: AGARWAL, K. B.
SCANNABLE VIRTUAL RAIL METHOD AND RING OSCILLATOR CIRCUIT FOR MEAUSRING VARIATIONS IN DEVICE CHARACTERISTICS
11/22/2006
Co-inventors: AGARWAL, K. B.
A METHOD OF SEPARATING THE PROCESS VARIATION IN THRESHOLD VOLTAGE AND EFFECTIVE CHANNEL LENGTH BY ELECTRICAL MEASUREMENTS
04/10/2006
Co-inventors: AGARWAL, K. B.
METHOD AND APPARATUS OF MEASURING DEVICE MISMATCHES
02/17/2006
Co-inventors: AGARWAL, K. B. Liu, Y. SIVAGNANAME, J.
TEST SYSTEM AND COOMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY
12/08/2005
Co-inventors: AGARWAL, K. B.
CHARACTERIZATION ARRAY AND METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION
04/17/2006
Co-inventors: AGARWAL, K. B.
CHARACTERIZATION ARRAY CIRCUIT
04/17/2006
Co-inventors: AGARWAL, K. B.
METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY
04/17/2006
Co-inventors: AGARWAL, K. B.
METHOD AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS
08/24/2005
Co-inventors: Joshi, R. KANJ, R. N.
SYSTEM AND METHOD FOR MEMORY ELEMENT CHARACTERIZATION
11/19/2004
Co-inventors: Agrawal, B. Feldmann, P. Nowicki, T. Swirszcz, G. M.
CIRCUIT FOR COMPUTING MOMENT PRE PRODUCTS FOR STATISTICAL ANALYSIS
10/27/2004
WAFER METHOD AND APPARATUS FOR PRE-PROCESSING MEASUREMENTS OF PROCESS AND ENVIRONMENT-DEPENDENT CIRCUIT PERFORMANCE VARIABLES FOR STATISTICAL ANALYSIS
02/15/2005
METHOD FOR DETERMINING THE LEAKAGE POWER FOR AN INTEGRATED CIRCUIT
03/10/2003
Co-inventors: Acar, E. DEVGAN, A. Liu, Y. SU, H.
METHOD FOR DETERMINING AND USING LEAKAGE CURRENT SENSITIVITIES TO OPTIMIZE THE DESIGN OF AN INTEGRATED CIRCUIT
03/05/2003
Co-inventors: Acar, E. DEVGAN, A.
METHOD AND SYSTEM FOR SHORT-CIRCUIT CURRENT MODELING IN CMOS INTEGRATED CIRCUITS
08/15/2002
Co-inventors: ARUNACHALAM, R. Acar, E.
METHOD AND SYSTEM FOR POWER NODE CURRENT WAVEFORM MODELING
06/17/2002
Co-inventors: Acar, E.
APPARATUS FOR MEASURING CAPACITANCE OF SEMICONDUCTOR DEVICE
04/30/2002
Co-inventors: Belluomini, W. Liu, Y. MCDOWELL, C.
METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION FOR POWER SUPPLIED BY A VOLTAGE ADAPTER
01/13/2002
Co-inventors: MCDOWELL, C.
DECOUPLING CAPACITOR SIZING AND PLACEMENT
05/21/2001
Co-inventors: SU, H.
APPARATUS AND METHOD FOR CLOCK SKEW MEASUREMENT
08/11/2000
Co-inventors: Boerstler, D.
METHOD AND APPARATUS FOR CHARACTERIZED PARASITIC CAPACITANCE BETWEEN INTEGRATED-CIRCUIT INTERCONNECTS
02/19/1997