Some useful links:
It's a Matter of Style: SystemVerilog for the e User
Some basic interview questions (topics are as per my experience!)
Verilog faq
Blocking vs Non-Blocking Statements, tasks Vs functions.
$monitor Vs $display Vs $strobe
Language constructs like setup, hold, recovery, force, release.
inter and intra assignment delays in blocking and non-blocking statements
flops, latches,
Digital logic faq
Moore and Mealy difference.
Sequence detectors.
Synchronizers.
Pulse shuttlers.
Specman faq
can be any junk question including difference between Units and Structures.
Language constructs.
eRM faq
define and explain eRM, its uses.
how do you verify a given module in block level. the complete flow.
sequences, virtual sequences.
integrating an existing eRM compliant eVC, eg., AHB eVC.
Coverage faq
code coverage: explain block, expression, fsm, toggle coverages.
functional coverage, cross, transition.
Gate Level Simulations faq
the flow of GLS.
concepts of setup, hold, recovery, clock skewing.
why GLS when you have formal and STA clean?
any specific bugs caught in GLS and not in RTL sims.
Perl Scripting
another junk area of asking questions. its an ocean! some basic concepts like opening, reading, closing of files.
reading lines, reading words, grep'ing for a pattern, mailing a result.
Protocols related faq
AHB spec related questions
like timing diagrams of read/write cycles with and without busy states.
master handover scenario timing diagram.
early bus termination.
USB 1.1 spec related questions
basic protocol questions
difficulties faced in verification.
verification completion criteria.
IrDA spec related queries
protocol, difficulties faced.
ATE faq
Automated Test Environment, also called ATPG : its flow, how do you setup the initial environment, tools used.
FPGA faq
the entire flow of bit file generation.
DCMs, DLL, Slices, Configurable-Logic blocks