About Me

I received the B.S. and M.S. degree in electrical engineering from Xi'an Jiaotong University, Xi'ian, China, in 1998 and 2001, respectively, and the Ph.D. degree in computer engineering from Texas A&M University, College Station, in 2005. I was enrolled in the Special Class for the Gifted Youth of Xi'an Jiaotong University at age 13. After graduation from Texas A&M, I co-founded Pextra Corp, an EDA startup company specializing in parasitic extraction and acquired by Mentor Graphics Corp. in 2009. From 2006 to 2014, I was a Research Staff Member at IBM Watson T.J. Research Center and Austin Research Lab developing IBM flagship physical design flow and tools including physical synthesis, interconnect synthesis, placement, optimization, timing and noise driven routing and flow integration. The tools are used to construct mainframe, storage and POWER series servers (P7/P7+/P8/Z, up to 5.5G Hz), gaming chips (Xbox, Cell Processor) and high performance ASICs from Cisco/Ericsson/Hisilicon/Brocade across technology nodes from 90 to 14 nm. I was a member of unit integration team for Torrent P7 Hub Chip (part of IBM PERCS Supercomputer), and a member of IBM SyNAPSE Project (neuronsynaptic chip). I have received five IBM Outstanding Technical Achievement Awards, one IBM Outstanding Contributor Award, and 4 IBM Research O-level accomplishment awards.

Currently I am a Engineering Group Director at Cadence Design Systems managing Clock Tree Synthesis and Early Global Route Tools used in Cadence digital implementation flow to enable chip designers to design better electronic chips with better performance/power/area in a shorter time. My work is released in Cadence latest digital implementation product Innovus and synthesis product Genus. I received Cadence Achievement Award in 2018, which is the highest award in Cadence (1 out of 1000+ people).

I have filed many patents with 50+ issued. I have published over 70+ conference and journal papers, and received the Best Paper Award at ISPD 2018, The Integration of VLSI 2017, ASPDAC 2007, the IEEE Circuits and System Society Outstanding Young Author Award at DAC 2007, three Best Paper Award Nominations at ISPD 2012, ICCAD 2008 and ISQED 2008, and two Best Paper Award Nominations at IEEE TCAD. I received the Technical Leadership Award from ACM SIGDA in 2011 for organizing power grid simulation contest, SRC Mahboob Khan Outstanding Industry Liaison/Associate Award in 2012, DAC Service Award in 2013, IEEE Region 5 Outstanding Individual Member Achievement Award in 2013 and 2014. In 2013, as the first winner from the industry (still the only one), I received IEEE CEDA Early Career Award, which is the top award for young researchers in EDA area. In 2015, the National Academy of Engineering has selected me to participate in the 2015 US Frontiers of EngineeringSymposium. The program is intended to select from among the nation’s top engineering talents in both academia and industry for ages 30-45. I have been serving as TPC sub-committee Chair or committee members for all major conferences in EDA area, such as DAC, ICCAD and DATE. I was the Guest Editor of VLSI Design Journal Special Issue “CAD for Gigascale SoC Design and Verification Solutions”. I was the Contest Chair of 2011 and 2012 TAU Power Grid Simulation Contest, Co-Chair of 2012 CAD Contest at ICCAD, Chair of 2013 CAD Contest at ICCAD and General Co-Chair of 2014 and 2015 DAC Ph.D. Forum. I was an Associate Editor of IEEE Transactions of Computer-Aided Design from 2014 to 2017. I joined Executive Committee of Design Automation Conference (DAC) since 2016 and currently serve as Vice Chair for DAC 2019.

I was on executive team of IEEE Central Texas Section and served as Vice Chair and Secretary of the Section. The Section won several Outstanding Large Section Awards in IEEE Region 5. I was the founding Chair of IEEE CEDA Chapter of Central Texas Section. When I was the Chapter Chair of IEEE CAS/SSC Chapter of Central Texas Section, the chapter won the IEEE Circuits and Systems Society 2014 Chapter of the Year Award, 2011 Region 1 to 7 Chapter of the Year Award and IEEE Solid State Circuits Society 2011 Outstanding Chapter Award. I was elevated to IEEE Fellow in 2018.

Here are two articles about me: IBM Blog - Profile of scientist and an article in IEEE Solid-State Circuits Magazine.