LIST OF ISSUED PATENTS FOR RAMNATH VENKATRAMAN
# U.S.Patent # Title
1 9158319 Closed-Loop Adaptive Voltage Scaling for Integrated Circuits
2 8589853 Total power optimization for a logic integrated circuit
3 8411399 Defectivity-immune technique of implementing MIM-based decoupling capacitors
4 8112734 Design Optimization with Adaptive Body Biasing
5 8044437, 8178909 Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements
6 7869251 SRAM based one-time-programmable memory
7 7440356 Modular design of multiport memory bitcells
8 7404154 Basic cell architecture for structured application-specific integrated circuits
9 7304874 Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas
10 7082067 Circuit for verifying the write speed of SRAM cells
11 7069535 Optical proximity correction method using weighted priorities
12 7042747 Ternary CAM bitcells
13 7006370 Memory cell architecture
14 7006369 Design and use of a spacer cell to support reconfigurable memories
15 6980462 Memory cell architecture for reduced routing congestion
16 6934174 Reconfigurable memory arrays
17 6828653 Method of forming metal fuses in CMOS processes with copper interconnect
18 6806551 Fuse construction for integrated circuit structure having low dielectric constant dielectric material
19 6778462 Metal-programmable single-port SRAM array for dual-port functionality
20 6664141 Method of forming metal fuses in CMOS processes with copper interconnect
21 6566171 Fuse construction for integrated circuit structure having low dielectric constant dielectric material
22 6442061 Single channel four transistor SRAM
23 6713381 Method of forming semiconductor device including interconnect barrier layers
24 6218302 Method for forming a semiconductor device
25 6174810 Copper interconnect structure and method of formation
26 6093966 Semiconductor device with a copper barrier layer and formation thereof
27 6077768 Process for fabricating a multilevel interconnect
28 6001726 Method for using a conductive tungsten nitride etch stop layer to form conductive
29 5814557 Method of forming an interconnect structure
30 5783485 Process for fabricating a metallized interconnect
31 5677244 Method of alloying an interconnect structure with copper
Additional Patent Publications
1) US 2013/0154109 A1: R. Venkatraman et al, Method of Lowering Capacitances of Conductive Apertures and an Interposer Capable of Being Reverse Biased to Achieve Reduced Capacitance.
2) US 2013/0166930 A1: T.Zhou et al., Reducing Power Consumption of Memory
3) US 2013/0166931 A1: R. Castagnetti et al., Reducing Power Consumption of Memory
4) US 2014/0028364 A1: R.Venkatraman et al, Critical Path Monitor Hardware Architecture for Closed Loop Adaptive Voltage Scaling and Method of Operation Thereof