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Welcome to RR Kumar Research Group
Digital Design Simulation Software (Deeds) Intradution || Installation || Basics of Components
Digital Design Simulation Software (Deeds) Intradution || Installation || Basics of Components
STLD Lab: Experiment 1 Logic Gates: AND, OR, NOT, XOR, XNOR, NAND, NOR
STLD Lab: Experiment 1 Logic Gates: AND, OR, NOT, XOR, XNOR, NAND, NOR
STLD Lab Experiment 2 Univerasal Gates
STLD Lab Experiment 2 Univerasal Gates
STLD Lab 3: Adders, Subtractors, Parallel adder/subtractors
STLD Lab 3: Adders, Subtractors, Parallel adder/subtractors
STLD lab 4: IC adders (74283) using Multisim
STLD lab 4: IC adders (74283) using Multisim
STLD lab Experiment 5: Comparators || 1-Bit || 2-Bit|| 4 Bit || IC 7485
STLD lab Experiment 5: Comparators || 1-Bit || 2-Bit|| 4 Bit || IC 7485
STLD Lab Experiment 6: Multiplexers || 2X1 || 4X1|| 8X1|| IC 74151
STLD Lab Experiment 6: Multiplexers || 2X1 || 4X1|| 8X1|| IC 74151
STLD Lab Experiment 7: Demultiplexers || 1X2 || 1X4 || 1X8 || Higher order Demux with Lower order
STLD Lab Experiment 7: Demultiplexers || 1X2 || 1X4 || 1X8 || Higher order Demux with Lower order
STLD Lab Experiment 8: Encoder ||Octal || Decimal || Priority || IC 74147 || IC 74148 | Priority
STLD Lab Experiment 8: Encoder ||Octal || Decimal || Priority || IC 74147 || IC 74148 | Priority
STLD lab Experiment 9 : Parity circuits || 4 Bit Parity || 9 Bit Parity ||
STLD lab Experiment 9 : Parity circuits || 4 Bit Parity || 9 Bit Parity ||
Digital Design Lab: CMOS NOT Gate Thoery and Simulation using Multisim
Digital Design Lab: CMOS NOT Gate Thoery and Simulation using Multisim
CMOS NAND Thoery and Simulation
CMOS NAND Thoery and Simulation
CMOS NOR Gate Theory an Simulation
CMOS NOR Gate Theory an Simulation
Digiatl Watch Project || 12 h Format || 24 h Format || Timer
Digiatl Watch Project || 12 h Format || 24 h Format || Timer
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