Asynchronous FIFO for Synchronization

Synchronization of asynchronous Process by asynchronous FIFO in programmed components (FPGA CPLD)

Often required synchronize two processes each of which is synchronized to a clock that is not synchronized to the other clock.

Not always is possible to use the IP of manufacture components companies especially when used in CPLD, The standard solution requires a clock input to the FIFO to each of the processes and uses ram elements.

The following proposed solution appropriate for all components and adapted especially to CPLD.

The FIFO does not need any clock input and is not based on memory but rather on the FLIP-FLOPS. This uniqueness makes the system the ability to work well in CPLD.

You are invited to simulate the planning addressed in this link:

Files located in the FifoCpld

S_FifoCpldCompTop.vhd the test file,

FifoCpldComp.vho the FIFO file.

The example is limited to FIFO depth of 4 BYTES.

With Pleasure I will help you in planning any programmed elements and synchronization issues in particular.

Mobile: 972-52-5597916

Email: ramiattas@gmail.com