Publications
Pritam Bhattacharjee. "SPICE Modeling of LDMOSFET Transistor." Journal of Semiconductor Devices and Circuits 2016; 3(1): 42–57p.
Bhattacharjee, Pritam, Arindam Sadhu, and Kunal Das. "A register-transfer-level description of synthesizable binary multiplier and binary divider." Microelectronics, Computing and Communications (MicroCom), 2016 International Conference on. IEEE, 2016.
Bhattacharjee, Pritam, Alak Majumder, and Tushar Dhabal Das. "A 90 nm leakage control transistor based clock gating for low power flip flop applications." Circuits and Systems (MWSCAS), 2016 IEEE 59th International Midwest Symposium on. IEEE, 2016.
Bhattacharjee, Pritam, and Alak Majumder. "LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder." Nanoelectronic and Information Systems (iNIS), 2016 IEEE International Symposium on. IEEE, 2016.
Bhattacharjee, Pritam, Bipasha Nath, and Alak Majumder. "LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications." 대한전자공학회 학술대회 (2017): 106-109. [Awarded for Best Paper - Golden Prize in ICEIC 2017, Phuket, Thailand]
Bhattacharjee, Pritam, Arijit Dey, Kunal Das, Swarnendu Kumar Chakraborty, and Rajat Subhra Goswami. "Implementation of Ternary Logic in QCA using SPICE Macro-Modeling." Journal of Engineering Technology (ISSN: 0747-9964) Volume 5, Issue 2, July, 2016, PP.143-155. [SCIE & Scopus Indexed]
Bhattacharjee, Pritam, Kunal Das, Arijit Dey, Debashis De, and Swarnendu Kumar Chakraborty. "Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell." Journal of Low Power Electronics 13, no. 2 (2017): 231-239. [ESCI & Scopus Indexed]
Bhattacharjee, Pritam, Alak Majumder, and Bipasha Nath. "A 23.52 μW/0.7 V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock." IEIE Transactions on Smart Processing & Computing 6.3 (2017): 220-227. [Korean SCI (KSCI)]
Bhattacharjee, Pritam, and Kunal Das. "SPICE Modeling for Metal Island Charged Confined Cellular Automata." Journal of Computational and Theoretical Nanoscience 14.5 (2017): 2326-2331. [Scopus Indexed]
Majumder, Alak, Bhattacharjee, Pritam, and Tushar Dhabal Das. "A Novel Gating Approach to Alleviate Power & Ground Noise in Silicon Chips." Journal of Circuits, Systems and Computers, 27(9): 1850146 (August, 2018) ©World Scientific. [SCIE & Scopus Indexed]
Alak Majumder, Pritam Bhattacharjee and Bipasha Nath. "Voltage Keeper Based Robust Flip-Flop for Low Power Applications" IPR Application No. (Kol): 201731044358.
Majumder, Alak, and Pritam Bhattacharjee. "Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip." Proceedings of 3rd IEEE-iNIS, Bhopal (December, 2017). [Special Session Paper, awarded with TCVLSI Student Travel Grant]
Majumder, Alak, and Pritam Bhattacharjee. “Variation Aware Intuitive Clock Gating to Mitigate On-Chip Power Supply Noise” International Journal of Electronics, ©Taylor & Francis Group 2018. DOI: 10.1080/00207217.2018.1460873 [SCI, SCIE & Scopus Indexed]
Sarkar, Dhiraj, Pritam Bhattacharjee, and Alak Majumder. "Data-Dependent Clock Gating approach for Low Power Sequential System." in MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems) available in: arXiv preprint arXiv:1806.02271 (2018).
Bhattacharjee, Pritam, and Alak Majumder. "A Variation Aware Robust Gated Flip-Flop for Power Constrained FSM Application" Journal of Circuits, Systems and Computers, 28(7): 1950108 (June, 2019) ©World Scientific. [SCIE & Scopus Indexed]
Bhattacharjee, Pritam, and Alak Majumder. "A Variable Delay Circuit to develop Identical Rise/Fall time in the Output" In: Maharatna K., Kanjilal M., Konar S., Nandi S., Das K. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 575. pp. 305-312. Springer, Singapore. [Awarded for Best Paper presentation in ICCACCS 2018] | DOI: 10.1007/978-981-13-8687-9_28
Bhattacharjee, Pritam, Dhiraj Sarkar and Alak Majumder. "A Variation Tolerant Data Dependent Clock Gating Approach for PSN Attenuated Low Power Digital IC" Ain Shams Engineering Journal ©Elsevier. [SCIE & Scopus Indexed]
Bhattacharjee, Pritam, Prerna Rana and Alak Majumder. "Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges" In Clock Synchronization, ISBN 978-1-83881-040-5 ©IntechOpen Limited, United Kingdom. [recognized by Web of Science - Book Citation Index ]
Bhattacharjee, Pritam, Bidyut K. Bhattacharyya and Alak Majumder. "A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time" Circuits, Systems, and Signal Processing ©Springer, 1-20. [SCIE & Scopus Indexed]
Bhattacharjee, Pritam, Bidyut K. Bhattacharyya and Alak Majumder. "Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application" Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials, Vol. 51, No. 2, 2021. [SCIE & Scopus Indexed]
Bhattacharjee, Pritam, Prerna Rana, Bidyut K Bhattacharyya, Alak Majumder "Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021. [SCIE & Scopus Indexed]