Biography

Vassilis Papaefstathiou comes from Thebes of the Boeotia prefecture, Greece. He holds a PhD, MSc, and BSc in Computer Science from the Computer Science Department of the University of Crete.

From June 2001 to September 2003 he worked as an IC Design and Verification Engineer in ISD S.A. and collaborated closely with ST Microelectronics. From October 2003 to April 2005 he was a Research Assistant in the Computer Architecture and VLSI Systems Laboratory at the Institute of Computer Science, FORTH. From September 2006 to February 2008 he was an Adjunct Instructor in the Computer Science Department, University of Crete where he taught the course of Digital Circuits Lab. From 2005 to 2013, he was a Research Engineer in the Computer Architecture and VLSI Systems Laboratory at the Institute of Computer Science, FORTH. From 2014 to 2016 he was a Post-doctoral Researcher in the Computer Science and Engineering Department at Chalmers University of Technology. Since October 2016 he is with FORTH. He has been heavily involved in several EU-funded research projects (EPI, eProcessor, EuroEXA, ExaNest, ExaNoDe, ECOSCALE, EuroServer, ERC MECCA, SHARCS, ENCORE, SARC, UNISIX, SIVSS) and has designed several FPGA-based hardware prototypes for multicore architectures and high-performance interconnects.

His research interests are on Parallel Computer Architecture, High-Performance Computing, Packet Switch Architectures, High-Speed Interconnects, Network Processing Architectures, Low-Power Datacenter Servers, Storage Systems, and Hardware Security with particular emphasis on cross-layer design and optimization.