Books

J. Fisher, P. Faraboschi, C. Young. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Morgan-Kaufmann (Elsevier). ISBN: 1-55860-766-8. Jan 2005. Book website is at http://www.vliw.org 

Conferences

• G. Saranathan, M. Foltin, A. Tripathy, M. Ziatdinov, A. Koomthanam, S. Bhattacharya. A. Ghosh, K. Roccapriore, R. Sukumar, P. Faraboschi. Towards Rapid Autonomous Electron Microscopy with Active Meta-Learning. Workshop on Artificial Intelligence and Machine Learning for Scientific Applications (AI4S). SC-W 2023: Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis. Nov 2023. 10.1145/3624062.3626085. 

• C. Bash, K. Bresniker, P. Faraboschi, T. Jarnigan, D. Milojicic and P. Wood, "Ethics in Sustainability," in IEEE Design & Test, 6/2023 doi: 10.1109/MDAT.2023.3283351.

• S. Sarkar, V. Gundecha, A. Shmakov, S. Ghorbanpour, A. Babu, P. Faraboschi, M. Cocho, A. Pichard, J. Fievez. "Multi-Agent Reinforcement Learning Controller to Maximize Energy Efficiency for Multi-Generator Industrial Wave Energy Converter". In Proceedings of the AAAI Conference on Artificial Intelligence (Vol. 36, No. 11, pp. 12135 - 12144), June 2022

• C. Xu, S. Bhattacharya, M. Foltin, S. Byna and P. Faraboschi, "Data-Aware Storage Tiering for Deep Learning," 2021 IEEE/ACM Sixth International Parallel Data Systems Workshop (PDSW), 2021, pp. 23-28, doi: 10.1109/PDSW54622.2021.00009.

• S. Huang et al., "A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper)," 2021 IEEE/ACM Programming Environments for Heterogeneous Computing (PEHC), 2021, pp. 20-26, doi: 10.1109/PEHC54839.2021.00008.

• D. Milojicic, P. Faraboschi, N. Dube and D. Roweth, "Future of HPC: Diversifying Heterogeneity," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 276-281, doi: 10.23919/DATE51398.2021.9474063.

• S. Huang et al., "Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators," 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021

• P Knebel, D Berkram, A Davis, D Emmot, P Faraboschi, G Gostin. A Gen-Z Chipset for Exascale Fabrics. 2019 IEEE Hot Chips 31 Symposium (HCS), 1-22

• Ankit, Aayush; Hajj, Izzat El; Chalamalasetti, Sai Rahul; Ndu, Geoffrey; Foltin, Martin; Williams, R Stanley; Faraboschi, Paolo; Hwu, Wen-mei W; Strachan, John Paul; Roy, Kaushik;. PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference. Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2019

• Ambrosi, Joao; Ankit, Aayush; Antunes, Rodrigo; Chalamalasetti, Sai Rahul; Chatterjee, Soumitra; El Hajj, Izzat; Fachini, Guilherme; Faraboschi, Paolo; Foltin, Martin; Huang, Sitao. Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. 2018 IEEE International Conference on Rebooting Computing (ICRC), 2018

• Faraboschi, Paolo; Computing in the Cambrian Era Plenary Talk - 2018 IEEE International Conference on Rebooting Computing (ICRC), 2018

• Xu, Cong; Lain, Antonio; Faraboschi, Paolo; Dube, Nic; Milojicic, Dejan; Feeding the Beast: High Performance Data Pipeline for Large-Scale Deep Learning A Collection of White Papers from the BDEC2 Workshop in San Diego, California 2019

• Milojicic, Dejan; Bresniker, Kirk; Campbell, Gary; Faraboschi, Paolo; Strachan, John Paul; Williams, Stan; Computing In-Memory, Revisited, 2018 IEEE 38th International Conference on Distributed Computing Systems (ICDCS) 1300-1309 2018 IEEE

• Ankit, Aayush; Hajj, Izzat El; Chalamalasetti, Sai Rahul; Ndu, Geoffrey; Foltin, Martin; Williams, R Stanley; Faraboschi, Paolo; Strachan, John Paul; Roy, Kaushik; Milojicic, Dejan S; PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference. ASPLOS 2019

• Ambrosi, Joao; Ankit, Aayush; Antunes, Rodrigo; Chalamalasetti, Sai Rahul; Chatterjee, Soumitra; El Hajj, Izzat; Fachini, Guilherme; Faraboschi, Paolo; Foltin, Martin; Huang, Sitao; Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. 2018 IEEE International Conference on Rebooting Computing (ICRC) 13-Jan 2018 IEEE

• Reto Achermann, Chris Dalton, Paolo Faraboschi, Moritz Hoffmann, Dejan Milojicic, Geoffrey Ndu, Alexander Richardson, Timothy Roscoe, Adrian L. Shaw, and Robert N. M. Watson. 2017. Separating Translation from Protection in Address Spaces with Dynamic Remapping. In Proceedings of the 16th Workshop on Hot Topics in Operating Systems (HotOS '17). ACM, New York, NY, USA, 118-124. DOI: https://doi.org/10.1145/3102980.3103000

• Zhan, J., Akgun, I., Zhao, J., Davis, A., Faraboschi, P., Wang, Y. and Xie, Y., 2016, October. A unified memory network architecture for in-memory computing in commodity servers. In Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on (pp. 1-14). IEEE.

• Deb, A., Faraboschi, P., Shafiee, A., Muralimanohar, N., Balasubramonian, R. and Schreiber, R., 2016, October. Enabling technologies for memory compression: Metadata, mapping, and prediction. In Computer Design (ICCD), 2016 IEEE 34th International Conference on (pp. 17-24). IEEE.

• El Hajj, I., Merritt, A., Zellweger, G., Milojicic, D., Achermann, R., Faraboschi, P., Hwu, W.M., Roscoe, T. and Schwan, K., 2016. SpaceJMP: programming with multiple virtual address spaces. ASPLOS XVI and ACM SIGOPS Operating Systems Review, 50(2), pp.353-368.

• Tootaghaj, D.Z., Farhat, F., Arjomand, M., Faraboschi, P., Kandemir, M.T., Sivasubramaniam, A. and Das, C.R., 2015, October. Evaluating the combined impact of node architecture and cloud workload characteristics on network traffic and performance/cost. In Workload characterization (IISWC), 2015 IEEE international symposium on (pp. 203-212). IEEE.

• Eisenman, A., Cherkasova, L., Magalhaes, G., Cai, Q., Faraboschi, P. and Katti, S., 2016, March. Parallel graph processing: Prejudice and state of the art. In Proceedings of the 7th ACM/SPEC on International Conference on Performance Engineering (pp. 85-90). ACM.

• P Faraboschi, K Keeton, T Marsland, DS Milojicic. Beyond Processor-centric Operating Systems. HotOS USENIX Workshop, 2015

• R. Giorgi, P. Faraboschi, An introduction to DF-Threads and their execution model. International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW), 2014

• A. Gupta, LV. Kalé, F.Gioachin, V.March, CH. Suen, BS. Lee, P. Faraboschi, R. Kaufmann, D. Milojicic: The Who, What, Why, and How of High Performance Computing in the Cloud. CloudCom (1) 2013: 306-314 (Best Paper Award)

• M. Solinas, RM Badia, F. Bodin, A.Cohen, P.Evripidou, P.Faraboschi, et al. The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. In Proceedings of Euromicro Conference on Digital System Design (DSD), IEEE, Los Alamitos, CA, pp 272-279, Sept. 2013

• A. Gupta, L. Kalé, D. Milojicic, P. Faraboschi, S.Balle. HPC-Aware VM Placement in Infrastructure Clouds. 2013 IEEE International Conference on Cloud Engineering (IC2E), Redwood City, CA, pp 11-20, Mar 2013

• A. Gupta, L.V. Kalé, D.S. Milojicic, P. Faraboschi, R. Kaufmann, V. March, F. Gioachin, CH Suen, and BS Lee. Exploring the performance and mapping of HPC applications to platforms in the cloud. In Proceedings of the 21st international symposium on High-Performance Parallel and Distributed Computing (HPDC '12). ACM, New York, NY, USA, 121-122

• J. Navaridas, B. Khan, S. Khan, P.Faraboschi, M.Lujan, "Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation," International Symposium on Networks-on-Chip, pp. 91-98, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip,pp. 91-98, Copenhagen, Denmark, May 9-11, 2012. [slides]

• A. Portero, A. Scionti, Z. Yu, P. Faraboschi, C. Concatto, L. Carro, A. Garbade, S. Weis, T. Ungerer, R. Giorgi, "Simulating the Future kilo-x86-64 core Processors and their Infrastructure", 45th Annual Simulation Symp. (ANSS12), Orlando, FL, Mar 2012.

• R. Giorgi (U. Siena), A. Scionti (U. Siena), A. Portero (U. Siena), P. Faraboschi (HP Labs). Architectural Simulation in the Kilo-core Era. Poster at 17th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012) London, UK, March 3–7 2012

• S. Li, K. Lim, P. Faraboschi, J. Chang, P. Ranganathan, and N. Jouppi. System-Level Integrated Server Architectures for Scale-Out Datacenters. In 44th Annual Intl. Symposium on Microarchitecture (MICRO44), Porto Alegre, Brazil Dec. 2011. IEEE/ACM

• D.Lugones, D. Franco, D. Rexachs, JC Moure, E. Luque, E. Argollo, A. Falcon D. Ortega, P.Faraboschi , "High-speed network modeling for full system simulation," Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on , vol., no., pp.24-33, 4-6 Oct. 2009

• J. Mogul, E. Argollo, M.Shah, P.Faraboschi. Operating system support for NVM+DRAM hybrid main memory. In Hot Topics in Operating Systems (HotOS USENIX Workshop, May 2009, Mount Veritas, Switzerland)

• P. Bryan, J. Beu, T. Conte, P. Faraboschi, D. Ortega. Our Many-core Benchmarks Do Not Use That Many Cores. In WDDD 2009. 8th Annual Workshop on Duplicating, Deconstructing, Debunking. Austin, TX. June 2009

• M. Monchiero, J-H Ahn, A. Falcon, D. Ortega, and P. Faraboschi. How to Simulate 1,000 cores. In dasCMP’08: Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, held in conjunction with MICRO-41. November 9, 2008, Lake Como, Italy [slides] (also published as HP Labs Technical Report HPL-2008-190)

• A. Falcón, P. Faraboschi, and D. Ortega, "An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters", in 2008 International Symposium on Performance Analysis of Systems and Software (ISPASS-2008), April 2008

• A. Falcón, P. Faraboschi, D. Ortega. Combining Simulation and Virtualization through Dynamic Sampling. 2007 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2007). Apr 2007. San Jose, CA

• S. Yacoub, J. Abad, P. Faraboschi, J., Burns, D. Ortega, V. Saxena. Document Digitization Lifecycle for Complex Magazine Collections. ACM Symposium on Document Engineering. Nov. 2005, Bristol, UK

• S. Yacoub, J. Abad, P. Faraboschi, J., Burns, D. Ortega. Chronos: a System for Digitally Recapturing Content from Scanned Magazines. HP Labs Technical Report. HPL-2005-100

• S. Yacoub, J. Abad, P. Faraboschi, J., Burns, D. Ortega. Semantic-Based Noise Reduction for Digital Documents. ICGST International Conference on Graphics, Vision and Image Processing (GVIP-05), Cairo, Egypt. Dec. 2005

• G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, J. Fisher. DELI: a new runtime control point. In 35th IEEE/ACM Annual Intl. Symposium on Microarchitecture (MICRO35), Istanbul, Turkey, Nov. 2002

• P. Faraboschi and F. Homewood. ST200: A VLIW Architecture for Media-oriented applications. Microprocessor Forum 2000. San Jose, CA, October 2000.

• P. Faraboschi, J. Fisher, G. Brown, G. Desoli, F. Homewood. Lx: A Technology Platform for Customizable VLIW Embedded Processing. In 27th International Symposium on Computer Architecture (ISCA27), Vancouver, Canada, June 2000. IEEE/ACM

• P. Faraboschi, G. Desoli, J. Fisher. Clustered Instruction-Level Parallel Processors. HPL Technical Report HPL-98-204. 1998

• J. Fisher, P. Faraboschi, and G. Desoli. Custom-Fit Processors: Letting Applications Define Architectures. In 29th Annual Int. Symposium on Microarchitecture (MICRO29), Paris, France, 12/1996. IEEE/ACM.

• De Gloria, P. Faraboschi, and M. Olivieri. A self-timed interrupt controller: a case study in asynchronous microarchitecture design. In Proc. ASIC 94, Rochester, NY, 9/1994. IEEE.

• A. Costa, A. De Gloria, P. Faraboschi, and A. Pagni. A tool for automatic synthesis of fuzzy controllers. In Proc. IEEE Int. Conference on Fuzzy Systems, Orlando, FL, 7/1994. IEEE.

• E. Avogadro, S. Commodaro, A. Costa, A. De Gloria, P. Faraboschi, F. Giudici, and A. Pagni. An optimized RISC instruction set for fuzzy applications. In Proc. IEEE International Conference on Fuzzy Systems, Orlando, FL, July 1994. IEEE.

• A. De Gloria and P. Faraboschi. Application specific parallel architectures. In Proc. IEEE Conference on Massively Parallel Computing Systems (MPCS), Ischia, Italy, May 1994. IEEE. Invited Paper.

• A. De Gloria, P. Faraboschi, and M. Olivieri. An evaluation system for distributed time VHDL simulation. In Proc. International Workshop on Parallel and Distributed Simulation (PADS94), pages 147-150, Edinburgh, UK, July 1994. IEEE/ACM/SCS.

• A. De Gloria, P. Faraboschi, and M. Olivieri. An analysis of dynamic scheduling techniques for symbolic applications. In 26th Annual International Symposium on Microarchitecture (MICRO26), Austin, TX, 12/1993. IEEE/ACM.

• A. De Gloria, P. Faraboschi, and M. Olivieri. A non-deterministic scheduler for a software pipelining compiler. In 25th Annual Int. Symposium on Microarchitecture (MICRO25), Portland, OR, November 1992. IEEE/ACM.

• A. De Gloria, P .Faraboschi, and M. Olivieri. Performance analysis of a parallel VLSI architecture for Prolog. Int. Workshop on VLSI for Artificial Intelligence and Neural Networks, Oxford, UK, 9/1992.

• P. Antognetti, A. De Gloria, P. Faraboschi, M. Olivieri, and A.Taddeo. VLSI design of a neural processing element for the Boltzmann Machine. In Proc. ASIC 92, Rochester, NY, September 1992. IEEE.

• P. Antognetti, P. Danielli, A. De Gloria, P. Faraboschi, and M. Olivieri. A standard cell set for delay insensitive VLSI design. In Proc. ASIC 92, Rochester, NY, September 1992. IEEE.

• A. De Gloria, P. Faraboschi, E. Guidetti, and M.Olivieri. ASIC and board design of a high performance parallel architecture. In Proc. EUROASIC 92, Paris, France, July 1992. IEEE.

• A. De Gloria, P. Faraboschi. A programmable instruction format extension to VLIW architectures. In Proc. COMPEURO 92, Den Haag, The Netherlands, May 1992. IEEE.

• A. De Gloria, P. Faraboschi, and G. Sensalari. VLSI design of domain specific architectures. In Proc. COMPEURO 91, Bologna, Italy, May 1991. IEEE.

• A. De Gloria and P. Faraboschi. An evaluation system for application specific architectures. In Proc. 23rd Annual Int. Symposium on Microarchitecture (MICRO23), Orlando, FL, 11/1990. IEEE/ACM.

• P. Faraboschi, D. Giusto, E. Guidetti, C. Regazzoni, and G. Vernazza. Knowledge-based multisensor data integration applied to road detection. In Proc. Mediterranean Electrotechnical Conference (MELECON89), Lisboa, Portugal, July 1989.

Journals & book collections

• P. Faraboschi, E. Frachtenberg, P. Laplante, D. Milojicic and R. Saracco, "Artificial General Intelligence: Humanity’s Downturn or Unlimited Prosperity," in Computer, vol. 56, no. 10, pp. 93-101, Oct. 2023, doi: 10.1109/MC.2023.3297739.

• C. Bash, P. Faraboschi, E. Frachtenberg, P. Laplante, D. Milojicic and R. Saracco, "Megatrends," in Computer, vol. 56, no. 7, pp. 93-100, July 2023, doi: 10.1109/MC.2023.3271428.

• P. Faraboschi, E. Frachtenberg, P. Laplante, D. Milojicic, R. Saracco. Digital Transformation: Lights and Shadows. Computer, 56(4), 123-130. 2023

• A. Justine, S. Serebryakov, C. Xu, A. Tripathy, S. Bhattacharya, P. Faraboschi, M. Foltin. "Self-learning Data Foundation for Scientific AI". In: Doug, K., Al, G., Pophale, S., Liu, H., Parete-Koon, S. (eds) Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation. SMC 2022. Communications in Computer and Information Science, vol 1690. Springer, Cham. https://doi.org/10.1007/978-3-031-23606-8_2, 2023

• M. Arlitt, T. Coughlin, P. Faraboschi, E. Frachtenberg, P. Laplante, D. Milojicic, N. Patel, R. Saracco "Future of the Workforce," in Computer, vol. 56, no. 1, pp. 52-63, Jan. 2023, doi: 10.1109/MC.2022.3203505.

• P. Faraboschi, E. Frachtenberg, P. Laplante, D. Milojicic and R. Saracco, "Virtual Worlds (Metaverse): From Skepticism, to Fear, to Immersive Opportunities," in Computer, vol. 55, no. 10, pp. 100-106, Oct. 2022, doi: 10.1109/MC.2022.3192702

• N. Dube, P. Faraboschi, D. Milojicic and D. Roweth, "Future of HPC: The Internet of Workflows" in IEEE Internet Computing, Sept.-Oct. 2021, pp. 26-34, vol. 25 DOI: 10.1109/MIC.2021.3103236

• P. Faraboschi, E. Frachtenberg, P. Laplante, K. Mansfield and D. Milojicic, "Technology Predictions: Art, Science, and Fashion," in Computer, vol. 52, no. 12, pp. 34-38, Dec. 2019, doi: 10.1109/MC.2019.2942286.

• Azriel, Leonid; Humbel, Lukas; Achermann, Reto; Richardson, Alex; Hoffmann, Moritz; Mendelson, Avi; Roscoe, Timothy; Watson, Robert NM; Faraboschi, Paolo; Milojicic, Dejan; Memory-side protection with a capability enforcement co-processor   ACM Transactions on Architecture and Code Optimization (TACO) 2019 ACM

• Bresniker, Kirk M; Faraboschi, Paolo; Mendelson, Avi; Milojicic, Dejan; Roscoe, Timothy; Watson, Robert NM;  Rack-Scale Capabilities: Fine-Grained Protection for Large-Scale Memories, Computer 2019 IEEE

• Gupta, A., Faraboschi, P., Gioachin, F., Kale, L.V., Kaufmann, R., Lee, B.S., March, V., Milojicic, D. and Suen, C.H., 2016. Evaluating and improving the performance and scheduling of HPC applications in cloud. IEEE Transactions on Cloud Computing, 4(3), pp.307-321

• Zhao, J., Li, S., Chang, J., Byrne, J.L., Ramirez, L.L., Lim, K., Xie, Y. and Faraboschi, P., 2015. Buri: Scaling big-memory computing with hardware-based memory expansion. ACM Transactions on Architecture and Code Optimization (TACO), 12(3), p.31.

• H Alkhatib, P Faraboschi, E Frachtenberg, H Kasahara, D. Lange, P. Laplante, A. Merchant, D. Milojicic, K. Schwan. What Will 2022 Look Like? The IEEE CS 2022 Report. IEEE Computer, Vol 48, N. 3, 2015

• B.Khan, D.Goodman, S.Khan, W.Toms, P. Faraboschi, M. Luján, I. Watson. Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems. Journal of Supercomputing. 2/2015.  Springer Science+Business Media New York 2015. DOI 10.1007/s11227-015-1383-2

• R. Giorgi, RM. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, et al. TERAFLUX: Harnessing dataflow in next generation teradevices, Microprocessors and Microsystems, April 2014, ISSN 0141-9331, http://dx.doi.org/10.1016/j.micpro.2014.04.001

• P. Faraboschi, TN Vijaykumar, Top Picks from the 2011 Computer Architecture Conferences. Guest Editor Introduction, IEEE Micro, Vol 32. N. 3, pp 3-6, 2012.

• J. Fisher, P. Faraboschi, C.Young. "VLIW Processors". Entry in "Encyclopedia of Parallel Computing". D. Padua (Ed.) 1st Edition., 2011, Springer. ISBN 978-0-387-09765-7

• E. Argollo, A. Falcon, P. Faraboschi, and D. Ortega. "Toward the datacenter: scaling simulation up and out". In "Processor and System-on-chip simulation", R. Leupers and O. Temam (Eds). 1st edition 2010, Springer. ISBN 978-1-4419-6174-7

• J. Fisher, P. Faraboschi, C. Young. "VLIW Processors: from Blue Sky to Best Buy". IEEE Solid State Circuit Magazine. Vol 1. N. 2, Spring 2009.

• E. Argollo, A. Falcon, P. Faraboschi, M. Monchiero, and D. Ortega. "COTSon: Infrastructure for full system simulation". In ACM SIGOPS Operating System Reviews. January 2009 [also published as HP Labs Technical Report HPL-2008-189]

• P. Faraboschi, J. Fisher, C. Young. Customizable Processors: Lofty Ambitions, Stark Realities. Chapter in “Customizable Embedded Processors”, P. Ienne and R. Leupers, Editors, Morgann-Kaufmann. San Mateo, CA. Jun 2006 (“Systems on Silicon” series)

• G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, J. Fisher. A new facility for dynamic control of program execution. Lecture Notes in Comp. Science, vol. 2491, pp 305-318, Oct 2002. Also presented at EMSOFT02 [slides]

• P. Faraboschi, J. Fisher, C. Young. Instruction Scheduling for Instruction Level Parallel Processors. Proceedings of The IEEE, Vol. 89, No. 11, November 2001.

• P. Faraboschi, G. Desoli and J. Fisher. VLIW Architectures for DSP and Multimedia Applications, Cover article in special issue: The Latest Word in Multimedia, IEEE Signal Processing, 15(2):59-85, 3/1998.

• A. Costa, A. De Gloria, P. Faraboschi, F. Passaggio. A VLSI Architecture for Hierarchical Motion Estimation. IEEE Trans. on Consumer Electronics, May 1995.

• A. Costa, A. De Gloria, P. Faraboschi, A. Pagni, and G. Rizzotto. Hardware solutions for fuzzy control. Proceedings of the IEEE, 83(3):422-435, March 1995.

• A. De Gloria and P. Faraboschi, "Design and performance evaluation of a parallel architecture for the Boltzmann machine," Proceedings of Twentieth Euromicro Conference. System Architecture and Integration, Liverpool, UK, 1994, pp. 629-636, doi: 10.1109/EURMIC.1994.390349.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Design and characterization of a standard cell set for delay insensitive VLSI design. IEEE Trans. on Circuit and Systems, 41(6):410-415, 6/1994.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Block placement with a Boltzmann Machine. IEEE Trans. on Computer-Aided Design of Integrated Circuit and Systems, 13(6):694-701, 6/1994.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Delay insensitive micro-pipelined combinational logic. Microprocessing and Microprogramming, 1993(39):447-454, November 1993.

• A. Costa, A. De Gloria, P. Faraboschi, G. Nateri, and M. Olivieri. An asynchronous approach to the RISC design of a micro-controller. Microprocessing and Microprogramming, 1993(38):447-454, October 1993.

• A. Costa, A. De Gloria, P. Faraboschi, and M. Olivieri. A parallel architecture for the color doppler flow technique in ultrasound imaging. Microprocessing and Microprogramming, 1993(38):545-551, October 1993.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Clustered Boltzmann Machines: Massively parallel architectures for constrained optimization problems. Parallel Computing, 19(3):163-175, March 1993.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Design of a massively parallel SIMD architecture for the Boltzmann Machine. Microprocessing and Microprogramming, 1993(37):144-147, February 1993.

• P. Danielli, A. De Gloria, P. Faraboschi, and M. Olivieri. A delay insensitive approach to VLSI design of a DRAM controller. Microprocessing and Microprogramming, 1993(37):140-143, February 1993.

• A. De Gloria, P. Faraboschi, and M. Olivieri. Efficient implementation of the Boltzmann Machine algorithm. IEEE Trans. on Neural Networks, 4(1):169-164, January 1993.

• A. De Gloria and P. Faraboschi. Massive parallelism in multi-level simulation of VLSI circuits. INTEGRATION: The VLSI Journal, 14(2):145-171, Dec. 1992.

• A. Costa, A. De Franciscis, A. De Gloria, and P. Faraboschi. Spectral estimation for 2-D Doppler ultrasound imaging. Electronics Letters, 28(23):2177-2179, November 1992.

• A. De Gloria, P. Faraboschi, and E. Guidetti. SYMBOL: A parallel incremental architecture for Prolog program execution. In J. Delgado-Frias and W. Moore, editors, VLSI for Artificial Intelligence and Neural Networks, pp. 133-142. Plenum, 1992.

• A. De Gloria, P. Faraboschi, and S. Ridella. A dedicated massively parallel architecture for the Boltzmann Machine. Parallel Computing, 18(1):57-75, January 1992.

• De Gloria and P. Faraboschi. A Boltzmann Machine approach to code optimization. Parallel Computing, 17(9):969-982, November 1991.

• De Gloria, P. Faraboschi, and E. Guidetti. A VLIW architecture for Prolog. IEEE MicroArch, 5(1):27-31, November 1991.