IBM Corporation; New York, USA – (April 2020 onwards)
I am currently working as a Z Systems Hardware Architect at IBM. Defining new instructions and functions, document the detailed operation of these functions, and design reviews for IBM Z Systems Architecture.
Michigan Technological University; Michigan, USA – (Feb 2014 – Mar 2020)
Role:
NSF Graduate Research Assistant (GRA)
Design Micro-architecture, Instruction Set Architecture, Addressing mode, Memory ordering, Memory model, Programing model development.
Development of Demand-Driven Execution (DDE) paradigm, DDE Simulator, Internal representation of Future Gated Single Assignment form for DDE & Control flow execution, DDE Assembly representation, DDE Accelerator.
Define new Micro-architecture and optimize the existing Micro-architecture.
Performance analysis of workloads to identify the bottleneck and provide improvement solutions.
Develop tools to enable diagnosis and debugging of performance issues.
Hand coding of ‘Livermore FORTRAN Kernels’ using DDE ISA in assembly language.
Exploiting instruction and data level Parallelism for extreme-scale machines
Summer Youth Program: Instructor for the course Stop the Hackers!
Graduate Teaching Assistant (GTA) / Grader for the course 'Systems Programming'.
Grading student’s project, programs, quizzes & resolving student’s queries regarding the subject.
Accomplishments:
Design and development of new execution paradigm which harvests both data-level & instruction-level parallelism.
The design of new Instruction Set Architecture (ISA) for demand-driven execution processor and the extended instruction set for MIPS32 architecture.
The design and development of a cycle-accurate simulator model of the new micro-architecture for demand-driven execution paradigm.
The design of new assembly language code based on Future Gated Single Assignment (FGSA) for demand-driven execution of imperative programs.
Development of new tools to enable diagnosis and debugging of performance issues for demand-driven execution simulator and performance analysis.
Sensing Technologies Pvt. Ltd.; Mumbai – (December 2011 - July 2013)
Role:
Research & Development Engineer (Electronics & Embedded systems).
Projects include Designing of Embedded System & firmware development for DC to DC converters 30A, Driver Information System (DIS) such as LCD clock, Temperature & Calendar system, Tell Tale display unit, Hour Meter, Controller Area Network (CAN) Bus controlled Tire pressure monitoring system (TPMS).
Design & Development of high power Automotive DC to DC converters with current ratings up to 30Amperes controlled using Digital Signal Processor (DSP).
CAN-Bus control Tire pressure monitoring system (TPMS). The system consists of Designing of LCD; CAN interface with the vehicle, LCD driving. The system gives real-time indications & warning.
CAN-Bus control driven TFT LCD, Driver Information System (DIS) with real-time indications & warning.
All projects comprise of use of different microcontrollers, Digital Signal Processor (DSP), CAN Bus and is being carried out according to ISO & TS standards.
The project is being carried out for different Automotive MNC’s like TATA Motors Ltd.
Advanced product quality planning (APQP) & Design Failure Mode Effects Analysis (DFMEA) is been considered for the product.
Accomplishments:
Exposure to different circuit design related to automotive electronics system used for DC to DC converters, Driver Information System (DIS), CAN Bus controlled Tire pressure monitoring system (TPMS).
Exposure to different Microcontrollers 8-bit, 16-bit, 32-bit; Digital Signal Processor (DSP) 8-bit, 16-bit & Controller Area Network (CAN) Bus, SAE J1939, TFT LCD.
Exposure to ISO & TS standards, Development & testing procedure involved in designing and manufacturing of large scale embedded products with stringent TS standards for automotive electronics.