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I co-designed following three ICs during the course of my Ph.D. These included my circuit design ideas that were published later in IEEE journals/conferences. I would like to thank CMC for providing access to leading IC manufacturing technologies through their prototype manufacturing program. They also provided EDA tools to design these ICs, compute infrastructure to run EDA tools, and test equipments to test these chips once fabricated.
1. ICFWTNM1
Date: 3 November, 2004
Design Team: Nitin Mohan, Wilson Fung, Derek Wright
Technology: TSMC CMOS 0.18 micron
Package: 80 CFP (Surface-mount)
CMC Run: 0404CF
Chip Details:
A full-custom 20Kb TCAM chip with priority encoder and test circuitry
Three novel match line sense amplifiers
Novel design of priority encoder
Total on-chip decoupling capacitance is approximately 1nF
Total transistor count (excluding decoupling capacitors) is approximately 400K
2. ICFWTAP3
Date: 6 August, 2003
Design Team: Andrei Pavlov, Nitin Mohan, Wilson Fung
Technology: TSMC CMOS 0.18 micron
Package: 84 PGA (Through-hole)
CMC Run: 0303CF
Chip Details:
A novel TCAM architecture for high-performance low-energy operation
A novel static TCAM cell with smaller chip area, lower leakage, and better hardness to soft-errors than the conventional TCAM cell
Several variations of the new and conventional TCAMs (144-bit words) to demonstrate the performance and energy advantages of the new scheme over the conventional TCAM
A DFT technique for detecting weak cells in embedded SRAMs with digitally programmable detection threshold
A novel design of priority encoder for high-performance and low-power TCAMs
3. ICFWTDR2
Date: 26 March, 2003
Design Team: Dave Rennie, Mohammad Maymandi-Nejad, Nitin Mohan
Technology: TSMC CMOS 0.18 micron
Package: 80 CFP (Surface-mount)
CMC Run: 0301CF
Chip Details:
A novel static Ternary Content Addressable Memory (TCAM) cell for low-energy and high-performance parallel table lookups
Two 144-bit words of the new and conventional TCAMs to demonstrate the performance and energy advantages of the new scheme over the conventional TCAM
Two 5Gbit/s CDR circuits: one with a linear phase detector, the other with a binary phase detector
A low voltage VCO and an SC amplifier
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