Publication
A. Book Chapters
1. YunSeop Yu, SungWoo Hwang, and David Ahn, “Modeling of Single-electron Transistors for Efficient Circuit Simulation and Design”, Handbook of Theoretical and Computational Nanotechnology, Chapter 5; Ed. M. Rieth and W. Schommers, Vol. X , pp. 319-362 (2006)
B. SCI Journals (total numbers: SCI 96, NonSCI 14)
2024(total numbers : SCI 0 )
1. S. S. Jeong, N. H. Kim, Y. S. Yu, "Comparison of Fall Detection Systems Based on YOLOPose and Long Short-Term Memory," J. Inf. Commun. Converg. Eng. Vol. 22, pp. 139-144, 2024. DOI: 10.56977/jicce.2024.22.2.139
2023(total numbers : SCI 4 )
1. T. J. Ahn, B. H. Choi, J.-W. Yu, Y. Kim, Y. S. Yu, " Effects of Thermal Treatment on DC Voltage-Driven Color Conversion in Organic Light-Emitting Diode," Micromachines, Vol. 14, No. 1, pp. 30, 2023. DOI:10.3390/mi14010030.
2. T. J. Ahn, B. H. Choi, J.-W. Yu, Y. S. Yu, " Dependence of the Color Tunability on the H2Pc Thickness in DC-Voltage-Driven Organic Light-Emitting Diodes," Appl. Sci., Vol. 13, No. 9, pp. 5315, 2023. DOI:10.3390/app13095315.
3. Y. S. Yu, K.-B. Kim, D. Jo, H.-C. Kim, J. Seo, "Current Research in Future Information and Communication Engineering 2022," Appl. Sci., Vol. 13, pp. 7258, 2023. DOI:10.3390/app13127258 .
4. J. H. Oh, Y. S. Yu, "Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD," Micromachines, Vol. 14, No. 10, pp. 1822, 2023. DOI: 10.3390/mi14101822 .
2022(total numbers : SCI 4 , NonSCI 1)
1. G. J. Lee, T. J. Ahn, S. K. Lim, and Y. S. Yu, "Electrical Characteristic Investigation of Logic Circuit Consisting of Modularized Monolithic 3D Inverter Unit Cell ," J. lnf. Commun. Converg. Eng. Vol. 20, No. 2, pp. 137-142, 2022. DOI: 10.6109/jicce.2022.20.2.137. (Non-SCI: Scopus)
2. J. H. Oh and Y. S. Yu, "Investigation of Tunneling Effect for a N-type Feedback Field-effect Transistor ," Micromachines, Vol. 13, No. 9, pp. 1329, 2022. DOI: 10.3390/mi13081329.
3. G. J. Lee and Y. S. Yu, "An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs," Micromachines, Vol. 13, No. 9, pp. 1524, 2022. DOI: /10.3390/mi13091524.
4. J. H. Oh and Y. S. Yu, "A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor ," Micromachines, Vol. 13, No. 10 , pp. 1625, 2022. DOI: 10.3390/mi13101625.
5. S. S. Jeong and Y, S. Yu, "Fall Detection System Based on Simple Threshold Method and Long Short-Term Memory: Comparison with Hidden Markov Model and Extraction of Optimal Parameters," Appl. Sci., Vol. 12, No. 21, pp. 11031, 2022. DOI: 10.3390/app122111031.
2021(tatal numbers: SCI 6, NonSCI 1 )
1. T. J. Ahn and Y. S. Yu, "Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET," Appl. Sci., Vol. 11, No. 1, pp. 277, 2021. DOI: 10.3390/app11010277 .
2. J. H. Oh and Y. S. Yu, "Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-effect Transistors ," J. Nanosci. Nanotechnol., Vol. 21, No. 8, pp. 4293-4297, 2021. DOI:10.1166/jnn.2021.19387.
3. T. J. Ahn and Y. S. Yu, "Interface Charge Effects of Monolithic 3D JLFET Inverter ," J. Nanosci. Nanotechnol. , Vol. 21, No. 8, pp. 4252-4258, 2021. DOI:10.1166/jnn.2021.19388.
4. N. T. Duong, C. Park, D. H. Nguyen, P. H. Nguyen, T. U. Tran, D. Y. Park, J. Lee, D. A. Nguyen, J. H. Oh, Y. S. Yu, M. S. Jeong, "Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor," Nano Today, Vol. 40, pp. 101263, 2021. DOI: 10.1016/j.nantod.2021.101263.
5. J. H. Oh and Y. S. Yu, "Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation," Micromachines, Vol. 12, No. 10, pp. 1174, 2021. DOI: 10.3390/mi12101174 10.3390/mi12101174 .
6. T. J. Ahn, S. K. Lim, and Y. S. Yu, "Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation," Appl. Sci., Vol. 11, No. 24, pp. 12151, 2021. DOI: 10.3390/appapp112412151.
7. Y. S. Yu, F. Najam, "Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistor for Circuit Simulation," J. lnf. Commun. Converg. Eng. Vol. 19, No. 4, pp. 263-268, 2021. DOI: 10.6109/jicce.2021.19.4.263. (Non-SCI: Scopus)
2020(tatal numbers: SCI 5)
1. C. H. Leong, M. W. Chuan, K. L. Wong, S. F. Najam Y. S. Yu, and M. L. P. Tan, "Compact Device Modelling of Interface Trap Charges with Quantum Capacitance in MoS2-based Field Effect Transistors," Semiconductor Science and Technology, Vol.35, No. 4, pp. 045023 , 2020. DOI: 10.1088/1361-6641/ab74f2.
2. F. Najam, S. Kim, Y. Choi, and Y. S. Yu, "Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect-Transistor," IEEE Trans. Electron Devices, Vol. 67, No. 5, pp. 2106-2112, 2020. DOI: 10.1109/TED.2020.2982262.
3. F. Najam and Y. S. Yu, "Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices ," Appl. Sci., Vol. 10, No. 13, pp. 4475, 2020. DOI: 10.3390/app10134475 .
4. J. H. Oh and Y. S. Yu, "Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation ," Micromachines, Vol. 11, No. 9, pp. 852, 2020. DOI: 10.3390/mi11090852 .
5. T. J. Ahn and Y. S. Yu, "Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs ," Micromachines, Vol. 11, No. 10, pp. 887, 2020. DOI: 10.3390/mi11100887.
2019(total numbers: SCI 5)
1. T. J. Ahn, R. Perumal, S. K. Lim, and Y. S. Yu, "Parameter Extraction and Power/Performance Analysis of Monolithic 3D Inverter (M3INV)," IEEE Trans. Electron Devices, Vol. 66, No. 2, pp. 1006-1011, 2019. DOI: 10.1109/TED.2018.2885817.
2. F. Najam and Y. S. Yu, "Impact of Quantum Confinement on Band-to-Band Tunneling of Line-Tunneling Type L –Shaped Tunnel Field-Effect-Transistor," IEEE Trans. Electron Devices, Vol. 66, No. 4, pp. 2010-2016, 2019. DOI: 10.1109/TED.2019.2898403.
3. J. C. Lee, T. J. Ahn, and Y. S. Yu, "Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire," J. Nanosci. Nanotechnol. Vol. 19, No. 10, pp. 6750-6754, 2019. DOI: 10.1166/jnn.2019.
4. F. Najam and Y. S. Yu, "Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region," Appl. Sci., Vol. 9, No. 18, pp. 3716, 2019. DOI: 10.3390/app9183716.
5. T. J. Ahn, B. H. Choi, S. K. Lim, and Y. S. Yu, "Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory," Micromachines, Vol. 10, No. 10, pp. 637, 2019. DOI: 10.3390/mi1010063.
2018(total numbers: SCI 5, NonSCI 1)
1. Y. S. Yu, “Compact Capacitance Model of Single-Gate Tunneling Field-Effect Transistor,” INFORMATION-An International Interdisciplinary Journal, Vol. 21, No. 1, pp. 325-332, 2018 (Non-SCI: Scopus).
2. T. J. Ahn and Y. S. Yu, "Electrical Characteristics of Ge/Si-Based Source Pocket Tunnel Field-Effect Transistors," J. Nanosci. Nanotechnol. Vol. 18, No. 9, pp. 5887–5892 , 2018. DOI: 10.1166/jnn.2018.15579.
3. J. C. Lee, T. J. Ahn, and Y. S. Yu, "Work-Function Engineering of Source-Overlapped Dual-Gate Tunnel Field-Effect Transistor," J. Nanosci. Nanotechnol. Vol. 18, No. 9, pp. 5925–5931, 2018. DOI: 10.1166/jnn.2018.15574.
4. F. Najam and Y. S. Yu, "Investigation of Corner Effect and Identification of Tunneling Regimes in L-Shaped Tunnel Field-Effect-Transistor," J. Nanosci. Nanotechnol. Vol. 18, No. 9, pp. 6575-6583, 2018. DOI: 10.1166/jnn.2018.15703.
5. J. C. Lee, T. J. Ahn, and Y. S. Yu, "Workfunction Engineering of A Pocket Tunnel Field-Effect Transistor with A Dual Material Gate," J. Korean Phys. Soc., Vol. 73, No.3, pp. 308-313, 2018. DOI: 10.3938/jkps.73.308.
6. F. Najam and Y. S. Yu, "Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope," Electronics, Vol. 7, No. 11, 275, 2018. DOI: 10.3390/electronics7110275.
2017(total numbers: SCI 2)
1. Y. S. Yu and F. Najam, "Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors," Journal of Electrical Engineering and Technology, Vol. 12, No 5, pp. 2014-2020, 2017.
2. K. Heo, K-S. Cho, J. Y. Choi, S. M. Han, Y. S. Yu, Y. Park, S. Kim, S. W. Hwang, and S. Y. Lee, "Temperature dependent Electrical Characterization of Amorphous Indium Zinc Oxide Thin-Film Transistors," IEEE Trans. Electron Devices, Vol. 64, No. 8, pp. 3183-3188, 2017.
2016(total numbers: SCI 4, NonSCI 3)
1. H. W. Kye, B. N. Song, S. E. Lee, J. S. Kim, S. J. Shin, J. B. Choi,Y. S. Yu and Y. Takahashi, “One electron-controlled multiple-valued dynamic random-access-memory,” AIP ADVANCES, Vol. 6, No. 2, pp.025320(6 pages), 2016.
2. Y. S. Yu and S.-H. Kim, “Fall detection algorithm using the fall feature parameters extracted from video and accelerometer sensor,” INFORMATION-An International Interdisciplinary Journal, Vol. 19, No. 2, pp.615-622, 2016 (Non-SCI: Scopus).
3. Y. S. Yu and S. K. Lim, "Device coupling effects of monolithic 3D inverters," J. lnf. Commun. Converg. Eng. Vol. 14, No. 1, pp.40-44, Mar. 2016 (Non-SCI).
4. S. F. Najam, M. L. P. Tan, and Y. S. Yu, "General SPICE modeling procedure for double-gate tunnel field-effect transistors," J. lnf. Commun. Converg. Eng. Vol. 14, No. 2, pp. 115-121, Jun. 2016 (Non-SCI).
5. S. H. Kim, H.-H. Choi, Y. S. Yu, "Improvements in adhesion force and smart embedded programming of wall inspection robot," J. Supercomput., Vol. 72, pp. 2635–2650, 2016.
6. Y. S. Yu, S. Panth, S. K. Lim, “Electrical Coupling of Monolithic 3-D Inverters," IEEE Trans. Electron Devices, Vol. 63, No.8, pp.3346-3349, 2016.
7. F. Najam, K. C. Lau,, C. S. Lim, and Y. S. Yu, and M. L. P. Tan, "Metal oxide-graphene field-effect transistor: interface trap density extraction model", Beilstein J. Nanotechnol., Vol. 7, pp. 1368-1376, 2016.
2015(total numbers: SCI 1)
1. F. Najam, M. L. P. Tan, R. Ismail, and Y. S. Yu, “2-Dimensional (2D) Transition Metal Dichalcogenide Semiconductor Field-Effect Transistors: The Interface Trap Density Extraction and Compact Model,” Semiconductor Science and Technology, Vol. 30, No. 7, pp. 075010(9 pages), 2015. (Selected to Highlights 2015 of Semiconductor Science and Technology)
2014(total numbers: SCI 4, NonSCI 2)
1. T. G. Kim, U. J. Kim, S. Y. Lee, Y. H. Lee, Y. S. Yu, S. W. Hwang, and S. Kim, “Barrier Height at the Graphene and Carbon Nanotube Junction,” IEEE Trans. Electron Devices, Vol. 61, No. 6, pp. 2203-2207, 2014.
2. Y. S. Yu, “A Unified Analytical Current Model for N-and P-Type Accumulation-Mode (Junctionless) Surrounding-Gate Nanowire FETs,” IEEE Trans. Electron Devices, Vol. 61, No. 8, pp. 3007-3010, 2014.
3. Y. S. Yu, “Compact Model of a pH Sensor with Depletion-Mode Silicon-Nanowire Field-Effect Transistor,” J. Semiconductor Technology and Science, Vol. 14, No. 4, pp. 451-456, 2014.
4. D. Lim, C. Park, N. H. Kim, S.-H. Kim, Y. S. Yu, “Fall-Detection Algorithm Using 3-Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model,” Journal of Applied Mathematics, Vol. 2014, Article ID 896030, 8 pages, 2014.
5. S. Panth, S. Samal, Y. S. Yu, and S. K. Lim, “Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs,” J. lnf. Commun. Converg. Eng., Vol. 12, No. 3, pp. 186-192, 2014. (Non-SCI)
6. S. Kim, J. Park, T. Kim, J. Shin, Y. S. Yu, and H.-H. Choi, "Improvement of Adhesion Force and Locomotion of Wall Climbing Robot using Physical Analysis," INFORMATION-An International Interdisciplinary Journal, vol. 17, no. 11, pp. 5513-5521, Nov. 2014. (Non-SCI: Scopus)
2013(total numbers: SCI 3, NonSCI 1)
1. Y. S. Yu, “Full-Range Analytic Drain Current Model for Depletion-Mode Long-Channel Surrounding-Gate Nanowire Field-Effect Transistor,” J. Semiconductor Technology and Science, Vol. 13, No. 4, pp. 361-366, 2013.
2. F. Najam, Y. S. Yu, K. H. Cho, K. H. Yeo, D.-W. Kim, J. S. Hwang, S. Kim, and S. W. Hwang, “Implicit Continuous Current-Voltage Model for Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors (SGMOSFETs) Including Interface Traps,” IEEE Trans. Electron Devices, Vol. 60, No. 8, pp. 2457-2463, 2013.
3. F. Najam, S. Kim, and Y. S. Yu, “Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope,” J. Semiconductor Technology and Science, Vol. 13, No.5, pp. 528-535, 2013.
4. Y. J. Yi and Y. S. Yu, “Emergency-Monitoring System Based on Newly-Developed Fall Detection Algorithm,” J. lnf. Commun. Converg. Eng., Vol. 11, No. 3, pp. 147-154, 2013. (Non-SCI)
2012(total numbers: SCI 4, NonSCI 1)
1. D. H. Kim, Y. W. Jeon, S. Kim, Y. Kim, Y. S. Yu, D. M. Kim, H.-I. Kwon, “A Physical Parameter-Based SPICE Models for InGaZnO Thin Film Transistors Applicable to Process Optimization and Robust Circuit Design,” IEEE Electron Device Letters, Vol. 33, No. 1, pp. 59-61, 2012.
2. T. G. Kim, J. S. Hwang, Y. S. Yu, M. G. Kang, and S. W. Hwang, “Single-String Carbon Nanotube Field Effect Transistors Fabricated by Two-Step Dielectrophoresis,” Japanese Journal of Applied Physics, Vol. 51, pp. 06FE02, 2012.
3. Y. S. Yu and H.-K. Park, “Analytic modeling of a depletion-mode surrounding-gate nanowire field-effect transistor,” J. Nanosicence Nanotechnogy, Vol. 12, No. 7, pp.5925-5929, 2012.
4. S. J. Kim, J. J. Lee, H. J. Kang, J. B. Choi,, Y.-S. Yu, Y. Takahashi, and D. G. Hasko, “One electron-based smallest flexible logic cell,” Appl. Phys. Lett. Vol. 101, No. 18, pp. 183101, 2012.
5. N. H. Kim, Y. S. Yu, “HFAT: Log-Based FAT File System Using Dynamic Allocation Method,” J. lnf. Commun. Converg. Eng., Vol. 10, No. 4, pp. 405-410, 2012. (Non-SCI)
2011(total numbers: SCI 4, NonSCI 1)
1. Y. J. Yi and Y. S. Yu, “PSPICE Modeling of Commercial ICs for Switch-Mode Power Supply (SMPS) Design and Simulation,” J. lnf. Commun. Converg. Eng., Vol. 9, No. 1, pp. 74-77, 2011(Non-SCI).
2. Y. S. Yu, N. Cho, S. W. Hwang, and D. Ahn, “Implicit Continuous Current-Voltage Model for Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors (SGMOSFETs) Including Interface Traps,” IEEE Trans. Electron Devices, Vol. 58, No. 8, pp. 2520-2524, 2011.
3. B. H. Hong, N. Cho, S. J. Lee, Y. S. Yu, L. Choi, Y. C. Jung, K. H. Cho, K. H. Yeo, D.-W. Kim, G. Y. Jin, K. S. Oh, D. Park, S.-H. Song, J.-S. Rieh, and S. W. Hwang, “Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge,” IEEE Electron Device Letters, Vol. 32, No. 9, pp. 1179-1181, 2011.
4. T.-W. Koo,D. S. Kim,J.-H. Lee,Y. C. Jung,J.-W. Lee, Y. S. Yu, S. W. Hwang,D. Whang, “Axial P-N Nanowire Gated Diodes as a Direct Probe of Surface-Dominated Charge Dynamics in Semiconductor Nanomater,”Journal of Physical Chemistry C, Vol. 115, No. 47, pp. 23552-23557, 2011.
5. Y. S. Yu and S. W. Hwang, “Analytic Model of A Silicon Nanowire pH Sensor,” J. Nanosicence Nanotechnogy, Vol. 11, No. 12, pp. 10809-10812, 2011.
2010((total numbers: SCI 6, NonSCI 1)
1. S. H. Son, S. W. Hwang, D. Ahn, J. I. Lee, Y. J. Park, and Y. S. Yu, “Fabrication and characterization of an enhancement mode planar resonant tunneling transistor”, IEEE Trans. Nanotechnolgy, Vol. 9, No. 1, pp. 123-127, 2010.
2. Y. S. Yu, “An analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure”, J. Semiconductor Technology and Science, Vol. 10, No. 2, pp. 152-159, 2010.
3. Y. S. Yu, N. Cho, J. H.n Oh, S. W. Hwang, and D. Ahn, “Explicit continuous current-voltage (I-V) models for fully-depleted surrounding-gate MOSFETs (SGMOSFETs) with a finite doping body”, J. Nanoscience and Nanotechnology, Vol. 10, No. 5, pp. 3316-3320, 2010.
4. J.-H. You, S.-H. Lee, C.-H. You, Y. S. Yu, and T.-W. Kim, “ Dependences of the electrical properties on the diameter and the doping concentration of the Si nanowire field effect transistors with a Schottky metal-semiconductor contact”, J. Nanoscience and Nanotechnology, Vol. 10, No. 5, pp. 3609-3613, 2010.
5. M.-G. Kang, J.-H. Ahn, J. Lee, D.-H. Hwang, H.-T. Kim, J.-S. Rieh, D. Whang, M.-H. Son, D. Ahn, Y.-S. Yu, and S.-W. Hwang, “Microwave Characterization of a Field Effect Transistor with Dielectrophoretically-Aligned Single Silicon Nanowire,” Japanese Journal of Applied Physics, Vol. 49, No. 6, pp. 06GG12, 2010.
6. Y. S. Yu, N. Cho, S. W. Hwang, and D. Ahn, “Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) with Localized Charges”, IEEE Trans. Electron Devices, Vol. 57, No. 11, pp. 3176-3180, 2010.
7. S. H. Choi, H.-K. Park, and Y. S. Yu, “Design and Implementation of Ubiquitous Sensor Network System for Monitoring the Bio-information and Emergency of the Elderly in Silver Town,” J. lnf. Commun. Converg. Eng.,Vol. 8, No. 2, pp.219-222, 2010. (Non-SCI)
2009(total numbers: SCI 6)
1. YunSeop Yu, Jung Hyun Oh, Hee Tae Kim, Yong Gyu Kim, Seung Hun Son, BumHo Choi, SungWoo Hwang, and Doyeol Ahn, “Simulation Method of Transmission-Type Radio-Frequency Single-Electron Transistor (RF-SET) by SPICE”, Semiconductor Science and Technology, Vol. 24, No. 2, pp.025020, 2009.
2. S.-J Kim, C.-K. Lee, R.-S. Chung, E.-S. Park, S.-J. shin, J.-B. Choi, Y.-S. Yu, N.-S. Kim, H. G. Lee, K.-H. Park, “Single-Electron-Based Flexible Multivalued Exclusive-OR Logic Gate”, IEEE Trans. Electron Devices, Vol. 56, No. 5, pp. 1048-1055, 2009.
3. H. T. Kim, Y. K. Kim, S. H. Son, Yun Seop Yu, D. Whang, D. Ahn and S. W. Hwang, “ Radio frequency electrical pulse characterization of defect states in a GaAs/AlGaAs narrow channel field effect transistor”, Semiconductor Science and Technology, Vol. 24, No. 8, pp. 085018, 2009.
4. Y. S. Yu, S. H. Lee, D. S. Kim, Y. C. Jung, S. W. Hwang, and D. Ahn, “A bottom-gate depletion-mode nanowire field effect transistor (NWFET) model including a Schottky diode model”, Journal of the Korean Physical Society, Vol. 55, No. 3, pp. 1162-1166, 2009.
5. SeHan Lee, YunSeop Yu, SungWoo Hwang, and Doyeol Ahn, “SPICE-compatible New Silicon Nanowire Field-Effect Transistors (SNWFETS) Model”, IEEE Trans. Nanotechnolgy, Vol. 8, No. 5, pp. 643-649, 2009.
6. Yun Seop Yu, Seong Ho Choi, Hyung-Kun Park, Changhoon Lee, Young-Sik Jeong, Sang-Hoon Kim, “A Power-, delay- and emergency-efficient protocol of ubiquitous sensor network systems for silver town applications”, J. Supercompt., 2009(DOI 10.1007/s11227-009-0320-7).
2008(total numbers: SCI 7, NonSCI: 1)
1. Jung Hyun Oh, D. Ahn, Y. S. Yu, and S. W. Hwang, “Green's function approach to transport through a gate-all-around Si nanowire under impurity scattering”, Phys. Rev. B., Vol. 77, No. 3, pp. 035313, 2008.
2. Yun Seop Yu, Se Han Lee, Jung Hyun Oh, Han Jung Kim, Sung Woo Hwang, and Doyeol Ahn, “A compact analytical current conduction model for depletion-mode n-type nanowire field-effect transistor (NWFET) with bottom-gate structure”, Semiconductor Science and Technology, Vol. 23, pp. 035025, 2008.
3. S. H. Son, M.G. Kang, S. W. Hwang, J. I. Lee, Y. J. Park, Y. S. Yu and D. Ahn, “Hybrid integration of GaAs/AlGaAs in-plane-gate resonant tunneling and field effect transistors”, Physica E, Vol. 40, No.6, pp. 2160-2162, 2008.
4. Y. K. Kim, H. T. Kim, S. H. Son, Y. S. Yu, D. Ahn, D. Whang, and S. W. Hwang, “Radio Frequency Pulse Response of an In-Plane-Gate Field Effect Transistor”, Journal of Physics: Conference Series, Vol. 109, pp. 012020, 2008 (Non-SCI).
5. Y. C. Jung, K. H. Cho, B. H. Hong, S. H. Son, D. S. Kim, D. Whang, S. W. Hwang, Y. S. Yu, and D. Ahn, “Fabrication and Characterization of Sidewall Defined Silicon On Insulator Single Electron Transistor”, IEEE Transactions on Nanotechnology, Vol. 7, No. 5, pp. 544-550, 2008.
6. S. J. Shin, Y. S. Yu, and J. B. Choi, “Multi-Valued Logic Circuits Using Hybrid Circuit Consisting of Three Gates Single-Electron Transistors (TG-SETs) and MOSFETs”, J. Nanoscience and Nanotechnology, Vol. 8, No. 10, pp. 4992-4998, 2008.
7. Y. C. Jung, D. S. Kim, B. H. Hong, K. H. Cho, S. W. Hwang, D. Ahn, Y. S. Yu, and B. H. Choi, “Fabrication and Characterization of Double Quantum Dot Structure”, J. Nanoscience and Nanotechnology, Vol. 8, No. 10, pp. 5009-5013, 2008.
8. D. S. Kim, Y. C. Jung, M. Y. Park, B. S. Kim, S. H. Hong, M. S. Choi, M. G. Kang, Y. S. Yu, D. Whang, and S. W. Hwang, “Electrical Characteristics of the Backgated Bottom-Up Silicon Nanowire FETs,” IEEE Transactions on Nanotechnology, Vol. 7, No. 6, pp. 683-687, 2008.
2007(total numbers: SCI 8)
1. Y. S. Yu, “A Multi-Gate Single-Electron Transistor Model for Circuits Simulation by SPICE”, Journal of the Korean Physical Society, Vol. 50, No. 3, pp. 739-743, 2007.
2. Y. S. Yu, D. H. Kim, J. D. Lee, B.-G. Park, S. W. Hwang, and D. Ahn, “Transport Spectroscopy of A Quantum Dot in Silicon-On-Insulator (SOI) MOSFET”, Journal of the Korean Physical Society, Vol. 50, No. 3, pp.885-888, 2007.
3. Yun Seop Yu, Seung Hun Son, Hee Tae Kim, Yong Gyu Kim, Jung Hyun Oh, Hanjung Kim, Sung Woo Hwang, Bum Ho Choi, and Doyeol Ahn, “A transmission-type radio-frequency single-electron transistor (RF-SET) with an in-plane-gate SET (IPG-SET)”, Jpn. J. Appl. Phy., Vol. 46, No. 4B, pp. 2592-2595, 2007.
4. YunSeop Yu and JungBum Choi, “A Half-Adder (HA) and A Full-Adder (FA) Combining Single-Electron Transistors (SETs) with MOSFETs”, Semiconductor Science and Technology, Vol. 22, pp. 647-652, 2007. (Selected to Highlights 2007 of Semiconductor Science and Technology)
5. YoungChai Jung, KeunHwi Cho, and SungWoo Hwang, David Ahn, and YunSeop Yu, “Observation of gate bias dependent interface coupling in thin silicon-on-insulator metal-oxide-semiconductor field-effect transistors”, J. Appl. Phys. Vol. 102, No. 1, pp. 034509, 2007.
6. YunSeop Yu and JungBum Choi, “New Adders Using Hybrid Circuit Consisting of Three-Gate Single-Electron Transistors (TG-SETs) and MOSFETs”, J. Nanoscience and Nanotechnology, Vol. 7, No. 11, pp. 4120-4125, 2007.
7. SeHan Lee, YunSeop Yu, SungWoo Hwang, and Doyeol Ahn, “Equivalent Circuit Model of Semiconductor Nanowire Diode by SPICE”, J. Nanoscience and Nanotechnology, Vol. 7, No. 11, pp. 4089-4093, 2007.
8. SeHan Lee, YunSeop Yu, SungWoo Hwang, and Doyeol Ahn, “Modeling of Semiconductor Nanowire Field Effect Transistors Considering Schottky Barrier Height Lowering”, Journal of the Korean Physical Society, Vol. 51, No. 96, pp. S298-302, 2007.
2006(total numbers: SCI 1)
1. S. H. Son, Y. S. Choi, S. W. Hwang, J. I. Lee, Y. J. Park, Y. S. Yu, D. Ahn, “Gate bias controlled NDR in an in-plane-gate quantum dot transistor”, Physica E, Vol. 32, No. 1-2, pp. 532-535, 2006.
2005 (total numbers: SCI 6)
1. Y. S. Yu, S. H. Kim, S. W. Hwang, and D. Ahn, “All-analytic surface potential model for SOI MOSFETs”, IEE Proceedings Circuits, Devices & Systems, Vol. 152, No. 2, pp. 183-188, 2005.
2. Y. S. Yu, “Parameter Extraction of Si-Based Single-Electron Transistor with Electrical Tunnel Barriers for Circuit Simulation”, Journal of the Korean Physical Society, Vol. 47 Supplement III, pp. S547-S551, 2005.
3. Y. S. Yu, S. H. Son, S. W. Hwang, N. K. Park, H. K. Park, J. H. Oh, and D. Ahn,”Simulation and Analysis of Radio-Frequency Single-Electron Transistor (RF-SET) by SPICE”, Journal of the Korean Physical Society, Vol. 47 Supplement III, pp. S543-S546, 2005.
4. S. H. Son, Y. S. Choi, K. H. Cho, S. W. Hwang, J. I. Lee, Y. J. Park, Y. S. Yu, and D. Ahn, “Single electron transport in GaAs/AlGaAs nano-in-plane-gate transistors”, Journal of the Korean Physical Society, Vol. 47 Supplement III, pp. S517-S521, 2005.
5. Y. S. Yu, H. W. Kye, B. N. Song, S-J. Kim, and J-B. Choi, “A New Multi-Valued (MV) Static Random Access Memory (SRAM) Cell with Single-Electron (SE) and MOSFET Hybrid Circuit”, Electronics Letters, Vol. 41, No. 24, pp. 1316-1317, 2005.
6. Y. S. Yu, S. W. Hwang, and D. Ahn, “Transient Modeling of Single-Electron Transistors for Efficient Circuit Simulation by SPICE”, IEE Proceedings Circuits, Devices & Systems, Vol. 152, No. 6, pp. 691-696, 2005.
2004 (total numbers: SCI 2)
1. Y. S. Yu, S. H. Kim, B. H. Choi, S. H. Hong, S. W. Hwang, and D. Ahn, “SPICE compatible floating-dot single-electron memory with a new description of SOI MOSFET including quantum mechanics effects”, Journal of the Korean Physical Society, Vol. 44, No. 1, pp. 117-120, 2004.
2. S. H. Son, K. H. Cho, K. M. Kim, Y. S. Yu, Y. J. Park, S. W. Hwang, D. Ahn, “Fabrication and Characterization of MESFET-type Quantum Devices”, J. Appl. Phys. Vol. 96, No. 1, pp. 704-708, 2004.
1996~2002 (total numbers: SCI 12)
1. S. W. Hwang, Y. S. Yu, W. I. Ha, T. G. Kim, C. K. Han, J. H. Park, M. S. Kim, E. K. Kim and S. K. Min, “Fabrication and characterization of modulation-doped-field-effect-transistors with antidot-patterned passivation layers”, Appl. Phys. Lett. Vol. 69, No. 13, pp. 1924-1926, 1996.
2. Y. S. Yu and S. W. Hwang, “Calculation of single electron inverter characteristics”, Journal of the Korean Physical Society, Vol. 30, s311, 1997.
3. Sung Woo Hwang, Tae-Woong Yoon, Dae Han Kwon, Yun Seop Yu and Ki Hyuck Kim, “A Physics-Based, SPICE (Simulation Program with Integrated Circuit Emphasis)-Compatible Non-Quasi-Static (Metal-Oxide-Semiconductor) Transient Model Based on the Collocation Method”, Jpn. J. Appl. Phy., Vol. 37, No. 2A, pp L119-L121, 1998.
4. D. H. Kwon, Y. S. Yu, K. H. Kim, T.-W. Yoon, and S. W. Hwang, “A New CAD-Compatible Non-Quasi-Static MOS Transient Model with Direct Inclusion of Depletion Charge Variations”, Journal of the Korean Physical Society, Vol. 33, pp. S192-S195, 1998.
5. H. S. Lee, Y. S. Yu, and S. W. Hwang, “Displacement Current Correction for the dc and Transient Simulation of Single Electron Transistors”, Journal of the Korean Physical Society, Vol. 33, pp. S266-S268, 1998.
6. Y. S. Yu, H. S. Lee, and S. W. Hwang, “SPICE Macro-Modeling for the Compact Simulation of Single Electron Circuits”, Journal of the Korean Physical Society, Vol. 33, pp. S269-S272, 1998.
7. Yun Seop Yu, Sung Woo Hwang, and Doyeol (David) Ahn, “Macromodeling of Single-Electron Transistors for Efficient Circuit Simulation”, IEEE Tran. Electron Devices, Vol. 46, No. 8, pp. 1667-1671, 1999.
8. Y. S. Yu, Y. I. Jung, J. H. Park, S. W. Hwang, and D. Ahn, “Simulation of Single-Electron/CMOS Hybrid Circuits Using SPICE Macro-modeling”, Journal of the Korean Physical Society, Vol. 35, pp. S991-S994, 1999.
9. Yun Seop Yu, Sung Woo Hwang, Du-Heon Song, and Kyeong Ho Lee, “Comments on “A Numerical Analysis of the Storage Times of Dynamic Random-Access Memory Cells Incorporating Ultrathin Dielectrics”“, IEEE Tran. Electron Devices, Vol. 47, No. 4, pp. 900-901, 2000.
10. Y. S. Yu, B. H. Choi, J. H. Oh, S. W. Hwang, and D. Ahn, “Single Electron Memory with Silicon Self-Assembled Quantum-Dots”, Journal of the Korean Physical Society, Vol. 39, pp. S27-S29, 2001.
11. B.H. Choi, Y. S. Yu, D.H. Kim, S.H. Son, K.H. Cho, S.W. Hwang, D. Ahn, B.G. Park, “Double-dot-like charge transport through a small size silicon single electron transistor”, Physica E, Vol. 13, pp.946-949, 2002.
12. Y. S. Yu, J. H. Oh, S. W. Hwang, and D. Ahn, “An equivalent circuit approach for the single electron transistor model for efficient circuit simulation by SPICE”, IEE Electronics Letters, Vol. 38, pp.850-852, 2002.
C. Domestic Journals(16편)
1. 유윤섭, 황성우, “3차원 결합 확률 분포를 고려한 단일전자 기본 논리 셀의 분석,” 대한전자공학회논문지, Vol. 33, No. 7, pp. 495-498, 1996.
2. 권대한, 유윤섭, 김기혁, 황성우, “새로운 CAD용 non-quasi-static MOS 과도상태 모델,” 대한전자공학회논문지, Vol. 34, No. 12, pp. 1000-1007, 1997.
3. 유윤섭, 김상훈, “회로시뮬레이션을 위한 단일전자 트랜지스터의 과도전류 모델링,” 대한전자공학회논문지, Vol. 40, No. 4, pp. 191-202, 2003.
4. 유윤섭, “SOI MOSFET의 모든 동작영역을 통합한 해석적 표면전위 모델,” 대한전자공학회논문지, Vol. 41, No. 2, pp. 9-15, 2004.
5. 박현식, 유윤섭, “박막저항기 특성에 미치는 제조공정인자의 영향,” 마이크로전자 및 패키징 학회지, Vol. 12, No. 1, pp. 1-7, 2005.
6. 유윤섭, 박현식, “고주파 단일전자 트랜지스터(RF-SET) 동작의 시뮬레이션 방법,” 대한전자공학회논문지, Vol. 42SD, No. 5, pp. 301-306, 2005.
7. 유윤섭, 김한정, “공핍 모드 N형 나노선 전계효과 트랜지스터의 전류 전도 모델,” 대한전자공학회논문지, Vol. 45SD, No. 4, pp. 375-382, 2008.
8. 유윤섭, “홉필드 신경회로망을 위한 단일전자 소자,” 대한전자공학회논문지, Vol. 45SD, No. 6, pp. 590-595, 2008.
9. 박철호, 임동하, 김남호, 유윤섭, “고령자 낙상에 의한 응급 상황의 4족 로봇 기반 알리미 시스템 설계 및 구현,” 한국정보통신학회논문지, Vol. 17, No. 4, pp. 781-788, 2013.
10. 김남호, 유윤섭, “3축 가속도 센서 데이터에 중력 방향 가중치를 사용한 낙상 인식 알고리듬,” 대한전자공학회논문지, Vol. 50, No. 6, pp. 254-259, 2013.
11. 김남호, 유윤섭, “은닉마르코프모델을이용한동영상기반낙상인식알고리듬대한전자공학회논문지, Vol. 50, No. 8, pp. 232-237, 2013.,”
12. 박철호, 유윤섭, “단순 임계치와 은닉마르코프 모델을 혼합한 영상기반 낙상 알고리즘,” 한국정보통신학회논문지, Vol. 18, No. 9, pp. 2101-2108, 2014.
13. 홍성현, 유윤섭, "양극성 이중 독립 게이트 실리콘 나노와이어 전계 효과 트랜지스터 설계," 한국정보통신학회논문지, Vol. 19, No. 12, pp. 2892-2898, 2015.
14. 안태준, 이시현, 유윤섭, "3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향," 한국정보통신학회논문지, Vol. 19, No. 12, pp. 2899-2904, 2015.
15. 이주찬, 안태준, 심언성, 유윤섭, "Si, Ge과 Si-Ge Hetero 터널 트랜지스터의 라인 터널링과 포인트 터널링에 대한 연구," 한국정보통신학회논문지, Vol. 21, No. 5, pp. 876-884, 2017.
16. 심언성, 안태준, 유윤섭, "터널링 전계효과 트랜지스터 4종류 특성 비교," 한국정보통신학회논문지, Vol. 21, No. 5, pp. 869-875, 2017.
17. 정승수, 김남호, 유윤섭, "장단기 메모리를 이용한 노인 낙상감지시스템의 정규화에 대한 연구," Vol. 25, No. 11, pp.1649-1654, 2021.
18. 유윤섭, "터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구," Vol. 26, No. 5, pp.682-687, 2022. DOI: 10.6109/jkiice.2022.26.5.682 .
D. 공학교육논문(7편)
1. 유윤섭, 김상훈, “실험교과목에 포함된 요소설계의 효과적인 운영에 대한 연구,” 한국실천공학교육학회논문지, Vol. 3, No. 1, pp.51-55, 2011.
2. 유윤섭, 김상훈, “고령친화산업체의 활성화를 위한 현장인력재교육사업 교과과정 사례 연구,” 한국실천공학교육학회논문지, Vol. 3, No. 2, pp.142-146, 2011.
3. 유윤섭, 유동상, “공학교육혁신을 위한 트랙제 교육과정 운영 방안 연구,” 한국실천공학교육학회논문지, Vol. 4 No. 2, pp.33-37, 2012.
4. 유윤섭, “산업체 수요에 기반한 산업의료원 교과목 운영 사례,” 한국실천공학교육학회논문지, Vol. 6, No. 1, pp.51-55, 2014.
5. 유윤섭, "FPGA 기반의 멀티미디어 재생기 설계 교육용 장비," 한국실천공학교육학회논문지, Vol. 6, No. 2, pp.91-97, 2014.
6. 조병우, 김남영, 유윤섭, " 센서 기반의 IOT 시스템의 FPGA 설계 교육용 장비," J. Pract. Eng. Educ. Vol. 8, No. 2, pp. 111-120, 2016.
7. 서보인, 유윤섭, "IMU 센서를 이용한 실내 위치인식 교육용 장비 및 응용," 한국실천공학교육학회논문지, Vol. 10, No. 2, pp.119-124, 2018.