Naveen Muralimanohar is currently a TPU architect at Google.

Publications:

Book:

Rajeev Balasubramonian, Norman Jouppi, Naveen Muralimanohar, “Multi-Core Cache Hierarchies”, Publisher – Morgan & Claypool 2011.

Book chapters:

  • Exercise questions to “Computer Architecture: A Quantitative Approach” (The Morgan Kaufmann Series) 5th Edition 2011.

  • Naveen Muralimanohar, Jung Ho Ahn, Norm Jouppi, “Memory modeling with CACTI” , “Processor and System-on-Chip Simulation”, Publisher –Springer 2010.

  • Ahn et al., “CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study”, “Low Power NoCs”, Publisher –Springer 2010.

Selective Conference and Journal Papers:

  1. Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. A. Nag et al. IEEE Micro 2018.

  2. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. A. Shafiee, A. Nag, N. Muralimanohar, et al., International Symposium on Computer Architecture (ISCA-43), 2016

  3. Improving Memristor Memory with Sneak Current Sharing. M. Shevgoor, N. Muralimanohar, R. Balasubramonian, Y. Jeon, International Conference on Computer Design (ICCD-34), 2015

  4. Overcoming the Challenges of Cross-Point Resistive Memory Architectures. C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie, International Symposium on High Performance Computer Architecture (HPCA-21), 2015

  5. Efficient Data Mapping and Buffering Techniques for Multi-Level Cell Phase-Change Memories. H. Yoon, J. Meza, N. Muralimanohar, N. P. Jouppi, O. Mutlu, ACM Transactions on Architecture and Code Optimization (TACO), 2014

  6. CACTI-IO: CACTI with Off-Chip Power-Area-Timing Models. N. P. Jouppi, A. B. Kahng, N. Muralimanohar, V. Srinivas, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2014)

  7. Design of Cross-point Metal-oxide ReRAM Emphasizing Reliability and Cost.", Dimin Niu, Cong Xu, Naveen Muralimanohar, Norm Jouppi, Yuan Xie, ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2013. Acceptance rate (26%).

  8. Understanding the Tradeoffs in MLC ReRAM Memory Design, Cong Xu, Dimin Niu, Naveen Muralimanohar, Norm Jouppi, Yuan Xie, Design Automation Conference (DAC), 2013. Acceptance rate (22%).

  9. CACTI-IO: CACTI with Off-chip Power-Area-Timing Models, Norm Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas, International Conference on Computer Aided Design (ICCAD),San Jose, November 2012. Acceptance rate (24%).

  10. Design Tradeoffs for High Density Cross-Point Resistive Memory.", Dimin Niu, Cong Xu, Naveen Muralimanohar, Norm Jouppi, Yuan Xie, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2012.

  11. Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Partha Ranganathan, “BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs”, International Symposium on Computer Architecture (ISCA-39), Oregon, June 2012. Acceptance rate (18%).

  12. Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, “LOT_ECC: Localized and Tiered Reliability Mechanisms for Commodity Memory Systems”, International Symposium on Computer Architecture (ISCA-39), Oregon, June 2012. Acceptance rate (18%).

  13. Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Partha Ranganathan, Norm Jouppi, Mattan Erez, “FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors”, IEEE Micro, Special Issue on the Top Picks from Microarchitecture Conferences (Micro’s Top Picks, 2012).

  14. Nathan Binkert, Al Davis, Norm Jouppi, Moray McLaren, Naveen Muralimanohar, Rob Schreiber, Jung Ho Ahn, “Optical High-Radix Switch Design”, IEEE Micro, Special Issue on the Top Picks from Microarchitecture Conferences (Micro’s Top Picks, 2012).

  15. N. Chatterjee, Naveen Muralimanohar, R. Balasubramonian, A. Davis, N. Jouppi. Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads” 18th International Symposium on High Performance Computer Architecture (HPCA-18), New Orleans, LA, February 2012. Acceptance rate (17%).

  16. Sheng Li, Ke Chen, Ming-Yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norm Jouppi, “System Implications of Memory Reliability in Exascale Computing” 24th Conference on Supercomputing (SC-24), Seattle, WA, November 2011. Acceptance rate (21%).

  17. Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, “Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems” International Symposium on Computer Architecture (ISCA-38), San Jose, June 2011. Acceptance rate (19%).

  18. Nathan Binkert, Al Davis, Norm Jouppi, Moray McLaren, Naveen Muralimanohar, Rob Schreiber, Jung Ho Ahn, “The Role of Optics in Future High Radix Switch Design” 38th International Symposium on Computer Architecture (ISCA-38), San Jose, June 2011. Acceptance rate (19%).

  19. Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Partha Ranganathan, Norm Jouppi, Mattan Erez, “FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors”, 17th International Symposium on High Performance Computer Architecture (HPCA-17), February 2011. Acceptance rate: 42/227 (18%).

  20. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, and Norm Jouppi, “Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support” 23rd Conference on Supercomputing (SC-23), November 2010. Acceptance rate: 51/253 (20%).

  21. Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi, “Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores” 37th International Symposium on Computer Architecture (ISCA-37), June 2010. Acceptance rate: 44/245 (18%).

  22. Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, “On the Scalability of Buses as On-chip Networks”, 16th International Symposium on High Performance Computer Architecture (HPCA-16), January 2010. Acceptance rate: 32/175 (18%).

  23. Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, “Non-Uniform Power Access for Large Caches with Low-Swing Wires”, 16th International Conference on High Performance Computing (HiPC-16), December 2009 (Best Paper Award). Acceptance rate: 49/261 (19%).

  24. Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, and Yuan Xie, “Leveraging 3D PCRAM Technologies to Reduce Checkpoint Overhead in Future Exascale Systems” 22nd Conference on Supercomputing (SC-22), November 2009. Acceptance rate: 59/261 (23%).

  25. Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer (Intel), Srihari Makineni (Intel), Donald Nowell (Intel), “Optimizing communication and Locality in a 3D stacked Reconfigurable Cache Hierarchy”, 15th International Symposium on High Performance Computer Architecture (HPCA-15), February 2009. Acceptance rate: 35/184 (19%).

  26. Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian, “Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory”, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17), October 2008. Acceptance rate: 30/159 (19%).

  27. Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, “Architecting Efficient Interconnects for Large Caches with CACTI 6.0”, IEEE Micro, Special Issue on the Top Picks from Microarchitecture Conferences (Micro’s Top Picks, Jan/Feb 2008)

  28. Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, “Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0”, 40th International Symposium on Microarchitecture (MICRO-40), December 2007. Acceptance rate: 35/167 (21%).

  29. Naveen Muralimanohar, Rajeev Balasubramonian, “Interconnect Design Considerations for Large NUCA Caches”, 34th International Symposium on Computer Architecture (ISCA-34), June 2007. Acceptance rate: 46/204 (23%).

  30. Naveen Muralimanohar and Rajeev Balasubramonian, “The Effect of Interconnect Design on the Performance of Large L2 Caches”, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), October 2006. Acceptance rate: 12/37 (32%).

  31. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, “Leveraging Wire Properties at the Microarchitectural Level”, (IEEE Micro) Vol. 26, No. 6, Nov/Dec 2006.

  32. Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, “Interconnect-Aware Coherence Protocols for Chip Multiprocessors”, International Symposium on Computer Architecture (ISCA-33), June 2006. Acceptance rate: 31/229 (14%).

  33. Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, “Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity”, International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2006. Acceptance rate: 24/81 (30%).

  34. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, “Wire Management for Performance and Power in Partitioned Architectures”, 11th International Symposium on High-Performance Computer Architecture (HPCA-11), February 2005. Acceptance rate: 28/181 (15%).

Interns Mentored:

Peng Gu, University of California

Ali Shafiee, University of Utah

Manju Shevgoor, University of Utah

Cong Xu, Penn State University

Dimin Niu, Penn State University

Hanbin Yoon, Carnegie Mellon University

Doe Hyun Yoon, University of Texas, Austin

Aniruddha Udipi, University of Utah, Salt Lake City

Xiangyu Dong, Penn State University

Owen Chen, MIT

Talks:

· Keynote on in-situ Computing in Near-Data Processing held in conjunction with MICRO 2015.

· Keynote on Crossbar memories in Memory Forum held in conjunction with ISCA 2014.

· HP Techcon (HP Internal conference 2014)

· HP Technical Seminar for HP-IT (2014) (audience of ~500 people)

· HP Techcon (HP Internal conference 2013)

· Indiana University Briefing, (HP customer talk 2011)

· Keynote in Workshop on Modeling, Benchmarking, and Simulation (MoBS 2011) held in conjunction with ISCA 2011

· International Symposium on Computer Architecture (ISCA 38, 2011)

· University of British Columbia (Invited Talk, 2010)

· Stanford, Palo Alto (Guest Lecture, May 2009)

· IBM Labs, Austin (Invited Talk, June 2008)

· HP Labs, Palo Alto (Invited Talk, May 2008)

· ATI Santa Clara, (Invited Talk, May 2008)

· AMD Boxborough, (Invited Talk, Jan 2008)

· Guest lecture, University of Utah, (March 2008)

· International Symposium on Microarchitecture (MICRO, 2007)

· International Symposium on Computer Architecture (ISCA 34, 2007)

· HP Labs, Palo Alto (May 2007)

· ATI Research Silicon Valley Inc., Santa Clara (Invited Talk, 2007)

· IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac­­2, 2006)

· International Symposium on Computer Architecture (ISCA 33, 2006)

· Workshop on complexity-effective design (WCED 2004) held in conjunction with ISCA-31

Professional Activities:

  • Contributed exercise questions to “Computer Architecture: A Quantitative Approach”

  • Program committee member MICRO 2015.

  • External review committee member HPCA 2014.

  • External review committee member MICRO 2012, 2013, 2014.

  • Program committee member CMP-MSI 2010, ISPASS 2011, HPCA 2012, MSPC 2012

  • Editorial Board Member of Journal on Low-Power Electronics (JOLPE)

  • Reviewer for HPCA 2005, ISPASS 2006, ACSAC 2007, MICRO 2007, HPCA 2008, ISLPED 2008, ICCD 2009, ACM Transactions on Design Automation of Electronic Systems, HiPC 2009, MICRO 2009, HPCA 2009, IEEE CAL, HPCA 2010, ISCA 2012, MICRO 2012, HPCA 2012, ISCA 2013, ISCA 2014

  • Web chair for Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMPMSI, 2008, 2009)

  • School of Computing architecture reading club coordinator for Fall 2007

  • Assisted with the registration process at ISPASS-07

  • Active member of IEEE