Please send comments or questions to: michaeldgodfrey@gmail.com.
This page provides links to publications and reports and a chronology of the fabricated chips which were designed in the Analog VLSI Systems Group in the Information Systems Laboratory in Electrical Engineering, Stanford University. This research started in the Fall of 1990.
We conduct research in Information and Computational Systems. Our objective is to create computational artifacts which satisfy optimality criteria as embedded systems. This objective is enabled by constructive mathematical engineering and, typically, by the availability of VLSI technology. The term constructive mathematical engineering is meant to encompass the theoretical developments in information theory (including signal processing, and various related special topics such as data compression, image analysis, etc.) which lead to optimal solutions for information processing systems. Due to the high computational performance and low cost of VLSI circuits these solutions can be constructed in a cost-effective manner.
Examples of work carried out in this program are:
Imaging systems based on signal processing and A/D conversion at the pixel level.
An analog VLSI model of the cochlear mechanism.
An analog wavelet transform chip.
A few of my talks and papers on the subject of Analog VLSI Systems:
A Stanford Seminar from 1995: "Mathematical Engineering and VLSI Systems."
A paper on VLSI device and circuit modeling: "CMOS Device Modeling for Subthreshold Circuits," IEEE Trans. on Circ. and Sys II; Analog and Digital Signal Processing, vol. 39, no. 8, Aug. 92.
"A VLSI Device Model for Analog Circuits." This second paper substantially supersedes the IEEE paper, and contains quite a lot of new information. An update was made on 5 May 2004. The changes in this update include several clarifications and updated Figures. There is an extended discussion of the history of measurement of the band gap energy and its temperature dependence. 26 September 2004: minor update to correct Table of Contents.
In addition, the Octave/Matlab files which are discussed in the paper are available in tar format. These files include the model as described in the paper and example analysis and plotting routines. These routines generated some of the plots shown in the paper. The code is old enough so that some changes will be needed for them to function correctly when using current versions of Octave or Matlab. The changes concern the plotting of the data.
A paper titled "The tanh Transformation" which describes some useful properties of the tanh function and indicates specifically how these properties can be useful in analog VLSI circuits.
Examples of results of this program are:
Imaging systems based on signal processing and A/D conversion at the pixel level. This work is reported by Boyd Fowler in his thesis, "CMOS Area Image Sensors with Pixel Level A/D Conversion."
Low-noise CMOS imaging circuits. These have been developed by Boyd Fowler and the technical team (Janusz Balicki, Steve Mims, Dana How, Michael D. Godfrey, and John Canfield) at Pixel Devices (acquired by Agilent Technologies, who subsequently licensed the technology to Fairchild Imaging, Inc.) This technology is in use in imaging products at Fairchild Imaging, Inc. Some of the techniques have been presented in "Low Noise Readout using Active Reset for CMOS APS," Boyd A. Fowler, Michael D. Godfrey, Janusz Balicki, and John Canfield, Proc. SPIE Vol. 3965, p. 126-135, May 2000, "Low FPN High Gain Capacitive Transimpedance Amplifier for Low Noise CMOS Image Sensors," Boyd A. Fowler, Janusz Balicki, Dana How, and Michael D. Godfrey, Proc. SPIE Vol. 4306, p. 68-77, May 2001, and "An Ultra Low Noise High Speed CMOS Linescan Sensor for Scientific and Industrial Applications," Boyd Fowler, Janusz Balicki, Dana How, Steve Mims, John Canfield, and Michael D. Godfrey, Proc. SPIE, Electronic Imaging Science and Technology, Jan. 2004, San Jose, CA. The presentation slides for the SPIE 2004 paper are also available.
This work has been further developed as described in "Reset Noise Reduction in Capacitive Sensors," Boyd Fowler, Michael D. Godfrey, and Steve Mims, IEEE TCAS-1, vol.53, No. 8, August 2006. The abstract from this paper reads:
Reset noise sets a fundamental detection limit for capacitive sensors. Many sensing circuits depend on accumulating charge on a capacitor as the sensing method. Reset noise is the noise that occurs when the capacitor is reset prior to the charge accumulation cycle. Therefore, it is important to understand the factors which determine reset noise, and how this noise may be mitigated. The purpose of this paper is to show how capacitive reset noise can be reduced during the reset cycle. We present and analyze three circuits that implement the basic methods for directly reducing capacitive reset noise. In addition, we present a time-domain technique for analysing the time-varying statistics of these circuits. This technique makes use of Ito calculus to obtain solutions to the time-varying stochastic differential equations. Theoretical noise calculations and Monte Carlo simulation results are presented for each technique. We show that theory and simulation yield similar results.
Finally, we show in the examples that reset noise may be reduced by a factor of 20 or more. We also refer to implemented sensor arrays which achieve these results.
Boyd Fowler's Ph.D. thesis: " CMOS Area Image Sensors with Pixel Level A/D Conversion" was a key work in the foundations of this methodology.
An analog VLSI model of the cochlear mechanism.
An analog wavelet transform chip.
The origins of this work were available on the web page of the Physics of Computation Group at Caltech, but this page is no longer active. If you are interested, take a look at other places where these ideas have been pursued, such as John Lazzaro's page where you will find the Chipmunk analog and digital VLSI design tools. Tobi Delbruck organized the Caltech Physics of Computation home page, which contained much interesting material. Tobi is now at INI in Zurich, and Carver Mead retired from Caltech in 2001. A good place to find out more these days is the Institute for Neuroinformatics at ETH/University of Zurich.
Papers on wavelet transforms mainly by Tim Edwards, including our paper from ICNN2 1995, "An Analog Wavelet Transform Chip," and a paper written by Tim, "Discrete Wavelet Transforms: Theory and Implementation" about the wavelet transform implementation on the Star Semiconductor SMP DSP chip. This implementation is of technical interest even though Star Semiconductor Inc. is no longer in business.
The versions of Gemini 2.7.2 and IRSIM 9.5 which we used under Redhat Linux 9 are available here. As far as we know, this is the latest version of Gemini. However, Tim Edwards has made IRSIM 9.7 available, which is likely a better choice. For many years we used a modified version of Magic 6.5.1 but it is best to obtain a current version from Cornell. Or, if you want the latest, you could try Tim Edwards current Magic site. This version of Magic contains all the changes that we had made, and a great deal more. In particular, it contains the file locking mechanism, which supports multiple users accessing the same design. We have moved to the latest 7.x version.
The OS/2 ports of Magic 6.5.1, Gemini 2.7.2 and IRSIM 9.5 have been available as magic-os2 and os2-adodons. I have not updated the distributions recently, and no longer know anyone who still uses OS/2.
The Table below lists the chips which have been fabricated through the MOSIS fabrication service
Notes on chips of special interest:
This chip produced a paper on subthreshold device modeling, and it produced a working model of the cochlea which resulted in a Ph.D. thesis by Neal Bhadkamkar.
This chip contains a very small, very low-cost single chip radio transmitter (implemented by Boyd Fowler) which could do lots of useful things around the home, or elsewhere.
This chip is a 64x64 phototransistor array which contains, at each pixel, analog light measuring circuits, a sigma-delta modulator, and A/D conversion. It has many performance and cost advantages over CDDs. This is Boyd Fowler's Ph.D. work. It has been reported on in the ISSCC Conference 1994, and the Ph.D. has been awarded.
This chip demonstrates a major performance improvement for the interconnect lines used in FPGA structures. It is the Ph.D. thesis work of Ivo Dobbelaere. It has been reported on in the ISSCC Conference 1995, and the Ph.D. has been awarded.
This is another Ph.D. project by Dana How which implements a high-performance asynchronous FPGA system. His Ph.D. has been awarded.
This chip was fabricated on a 0.35um process. It contains approximately 1.3 million transistors. The chip is fully functional and will be the subject of a number of Ph.D.'s and publications. Check out Abbas El Gamal's Group for more information.