Integrated Circuits Project 2020
Goal:
The goal of this project is to design and layout of different AOI logic designs.
They are key components in CMOS combinational logic and control path.
In this project you are asked to design, simulate and then implement it to do layout, and characterize different AOI logic designs.
Design Requirements:
1. The students will form groups of no more than five for this project. Make sure that the work is divided equally between the members of each group.
2. Each group work together in the design, analysis and simulation, but each student has to write his own report separably and each student send his own report, don't copy from each other, only the results should be the same for each group.
3. Each group pick one of the designs on this Google Sheet, don't change in the file, changes can be tracked, just pick one design.
4. Sketch the circuit directly from the expression for Y. From inspection of the circuit, reduce the number of transistors to minimum.
5. There are many ways that you can implement an AOI. Check online resources and select one type of AOI that you think can provide the best power, area, or delay tradeoff. Students with minimum delay, minimum power, or minimum layout area will obtain 10% bonus credit for the project.
6. You can use one of those VLSI tools:
or you may choose any other design tools.
7. Use the Power Point Schematic Template for the schematic drawing for your report.
8. Use 3V power supply and a 500fF load capacitor in the output for your spice simulations.
Due Date:
- The complete report is due on May 31, 2020.
- Reports (report for each student) must be sent by email to my email: mfarahat@zu.edu.eg. NEW
Deliverables:
- There will be an online interview with each group to discuss their work.
- A written report that contains but not limited to the following items.
1. Give an introduction on the history of Integrated Circuits and its importance, in not more than two pages.
2. Give a detailed explanation on how you designed the CMOS logic gate circuit for each step:
The design of the circuit schematic.
The calculation of tr , tf , tpHL , tpLH , tp .
The calculation of static power dissipation Ps when Vin=0,
The calculation of dynamic power dissipation Pd when the circuit is operated at 500 MHz.
3. Waveforms from PSPICE simulations that shows the functionality of the AOI. Clearly show all the data (inputs and outputs) on the waveforms.
4. Using SPICE, measure the worst case switching energy. Use a 500fF load capacitor in your energy and delay measurement in the PSPICE simulation. Assume the input rise time is very fast (10ps or less).
5. Complete layout with X and Y dimensions and the total area.
6. Original SPICE file (circuit netlist).
7. Summarize your layout area, measured switching energy, and measured delay in a table.
8. Compare between the hand analysis and the simulation results in a table.
9. A table showing the hour spent for each task by each member of the group.