Hypervisor-based Virtualization

In this article, I explain some of the internal details of how hypervisor-based virtualization is implemented on computers (PC, workstation and server) that are based on the x-86 (32 bit and 64 bit) instruction set architecture (ISA)[1]. A hypervisor controls the hardware resources and exposes a virtualized version of the ISA and the hardware to virtual machines (VM). Hence there is a need for understanding of some of the internals of the hardware architecture, including the ISA. I will cover CPU, memory, interrupt and IO virtualization focusing on Linux/QEMU/KVM as the hypervisor.

The rest of the article is organized as follows:

• Some of the x86 ISA basics[2]:

  • Privilege Levels and Registers

  • Interrupts, Faults, Traps and IO

  • Memory Management.

• A brief introduction on hypervisor-based full virtualization.

• CPU Virtualization

• Memory Virtualization

• IO and Interrupt Virtualization.

[1] Note, I am not covering every single aspect of the ISA, only those required for explaining the internals of virtualization.

[2] The concepts discussed may be applicable to RISC (reduced instruction set computing), such as the ARM (Advanced RISC Architecture) used in various systems, especially mobile devices.