My current research focus is the architecture of a CPU and SoC specifically tailored for use in the datacentre, encompassing a specialized microarchitecture, memory hierarchy, and networking functions. In general, my interests revolve around the shift away from the hunt for instruction-level parallelism, to the integration of specialized silicon units into one chip.
mark /dot/ sutherland /at/ epfl /dot/ ch
EPFL IC ISIM PARSA INJ 239 (Bât. INJ) Station 14 CH-1015 Lausanne Switzerland
Doctor of Philosophy (PhD), École Polytechnique Fédérale de Lausanne (EPFL), Sept. 2016 - present
Master of Applied Science (MASc.), University of Toronto, Sept. 2014 - Jul. 2016
- Supervisor: Prof. Natalie Enright Jerger, Percy Hart Professor of Electrical and Computer Engineering
Bachelor of Applied Science (BApSc.) - Engineering Science, University of Toronto, Sept. 2009 - Jun. 2014
- Thesis: Security: At What Price? Investigating the Hardware Cost of Physical Layer Security in Communication Systems
- Design Guidelines for High-Performance SCM Hierarchies
Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel, Mark Sutherland, Edouard Bugnion, Babak Falsafi, and Dionisios Pnevmatikatos.
In Proceedings of the 2018 International Symposium on Memory Systems (to appear), MEMSYS'18, October 1st 2018.
Current draft available: 1801.06726v3. Revised: 11 May 2018
Mark Sutherland and Natalie Enright Jerger.
In Proceedings of the 1st International Workshop on Architecture for Graph Processing (AGP-1), 2017.
Mark Sutherland, Ajaykumar Kannan, and Natalie Enright Jerger.
In Proceedings of the 2nd Data Prefetching Championship (DPC-2), 2015.
Mark Sutherland, Joshua San Miguel, and Natalie Enright Jerger.
In Proceedings of the Workshop on Approximate Computing Across the System Stack (WAX), 2015.