Research

My area of interest are Digital VLSI Design, ASIC/FPGA Implementation, Arithmetic Architectures, Algorithmic Synthesis, SoC Design, Hardware-Software Co-Design, DSP Implementation on VLSI.

Publications: Google Scholar DBLP

Journals:

  1. Manish Kumar Jaiswal, and Hayden K.-H. So, "PACoGen: A Hardware Posit Arithmetic Core Generator", IEEE Access, vol. 7, pp. 74586-74601, June 2019.

  2. Manish Kumar Jaiswal, and Hayden K.-H. So, "Design of Quadruple Precision Multiplier Architectures with SIMD Single and Double Precision support", Elsevier Integration, vol. 65, pp. 163-174, March 2019.

  3. Farkhanda Syed, Zahid Ullah, and Manish Kumar Jaiswal, "Fast Content Updating Algorithm for an SRAM based TCAM on FPGA”, IEEE Embedded Systems Letters, vol. 10 , no. 3, pp. 73-76, Sep 2018.

  4. Manish Kumar Jaiswal, and Hayden K.-H. So, "An Unified Architecture for Single, Double, Double-Extended and Quadruple Precision Division", Circuits, Systems and Signal Processing (CSSP), Springer, vol. 37,no. 1, pp. 383-407, Jan 2018.

  5. Manish Kumar Jaiswal, and Hayden K.-H. So, "Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division", IEEE Transactions on Circuit and Systems 1:Regular Papers (IEEE TCAS1), vol. 64, no. 02, pp. 386-398, Feb. 2017.

  6. Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden K.-H. So, M. Balakrishnan, K. Paul, Ray C.C. Cheung, "Configurable Architectures for Multi-Mode Floating Point Adder", IEEE Transactions on Circuit and Systems 1:Regular Papers (IEEE TCAS1), vol. 62, no. 8, pp. 2079-2090, Aug 2015.

  7. Z. Ullah, Manish Kumar Jaiswal and Ray C.C. Cheung, "Z-TCAM: An SRAM-based Architecture for TCAM", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 2, pp. 402-406, Feb 2015.

  8. Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan, and K. Paul, "Unified Architecture for Double / Two-Parallel Single Precision Floating Point Adder", IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 61, no. 7, pp. 521-525, July 2014.

  9. Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan, and K. Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", Circuits, Systems and Signal Processing (CSSP), Springer, vol. 33, no. 11, pp. 3499-3526, 2014.

  10. Z. Ullah, Manish Kumar Jaiswal and Ray C.C. Cheung, "E-TCAM: An Efficient SRAM-based Architecture for Ternary Content Addressable Memory", Circuits, Systems and Signal Processing (CSSP), Springer, vol. 33, no. 10, pp. 3123-3144, 2014.

  11. Manish Kumar Jaiswal, Ray C.C. Cheung, "Area-efficient Architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support", Microelectronics Journal, Elsevier, vol. 44, no. 5, pp. 421-430, May 2013.

  12. Manish Kumar Jaiswal, Ray C.C. Cheung, "VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique", Circuits, Systems and Signal Processing (CSSP), Springer, vol. 32, no. 1, pp. 15-27, Feb 2013.

  13. Manish Kumar Jaiswal, Ray C.C. Cheung, "High Performance FPGA Implementation of Double Precision Floating Point Adder/Subtractor", , International Journal of Hybrid Information Technology, SERSC, vol. 4, no. 4, pp. 71-80 , Oct-2011, ISSN 1738-9968.

  14. Manish Kumar Jaiswal, Nitin Chandrachoodan, "FPGA Based High Performance and Scalable Block LU Decomposition Architecture", IEEE Transactions on Computers, vol. 61, no. 1,pp. 60-72, Jan-2012.

  15. Manish Kumar Jaiswal, "Acceleration of Correlation Matrix on Heterogeneous Multi-Core CELL-BE Platform", International Journal of Advanced Science & Technology, SERSC, vol. 27, pp. 1-14, Feb-2011, ISSN 2005-4238.


Conferences:

  1. Manish Kumar Jaiswal and Hayden K.-H. So, "Architecture Generator for Type-3 Unum Posit Adder/Subtractor", IEEE International Symposium on Circuits and Systems (ISCAS 2018), pp. 1-5, Florence, Italy, May 2018.

  2. Manish Kumar Jaiswal and Hayden K.-H. So, "Universal Number Posit Arithmetic Generator on FPGA", Design Automation and Test (DATE 2018), pp. 1159-1162, Dresden, Germany, Mar 2018.

  3. Manish Kumar Jaiswal and Hayden K.-H. So, "DSP48E Efficient Floating Point Multiplier Architectures on FPGA", 30th Internationa Conference on VLSI Design & 16 th International Conference on Embedded Systems (VLSID), pp. 1-6, Hyderabad, India, Jan 2017.

  4. Ho-Cheung Ng, M. Wang, B. M.-F. Chung, B. S. C. Varma, Manish Kumar Jaiswal, K. K. Tsia, A. H.-C. Shum and H. K.-H. So, "Real-time Object Detection and Classification for High-Speed Asymmetric-Detection Time-Stretch Optical Microscopy on FPGA", The International Conference on Field Programmable Technology (FPT’16), pp. 261-264, Xi'an, China, Dec-2016.

  5. M. Wang, Ho-Cheung Ng, B. M.-F. Chung, B. S. C. Varma, Manish Kumar Jaiswal, Sam M.H Ho, K. K. Tsia, A. H.-C. Shum and H. K.-H. So, "High-throughput Cellular Imaging with High-Speed Asymmetric-Detection Time-Stretch Optical Microscopy under FPGA platform", International Conference on Reconfigurable Computing and FPGAs (ReConFig’16), pp. 1-6, Cancum, 2016.

  6. Manish Kumar Jaiswal and Hayden K.-H. So, "Dual-Mode Double Precision Division Architecture", IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, Abu Dhabi, UAE, Oct 2016.

  7. M. Wang, Ho-Cheung Ng, B. M.-F. Chung, B. S. C. Varma, Manish Kumar Jaiswal, K. K. Tsia, A. H.-C. Shum, H. K.-H. So, "In-situ Object Detection and Classification on FPGA for Asymmetric-Detection Time-Stretch Optical Microscopy", International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), PhD forum, Hong Kong, July-2016.

  8. Manish Kumar Jaiswal and Hayden K.-H. So, "Taylor Series Based Architecture for Quadruple Precision Floating Point Division", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 518-523, Pittsburgh, USA, July 2016.

  9. Manish Kumar Jaiswal and Hayden K.-H. So, "Architecture for Quadruple Precision Floating Point Division with Multi-Precision Support ", The 27th Annual IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 239-40, London, July 2016.

  10. Zahid Ullah, Manish Kumar Jaiswal, Ray C.C. Cheung, and Hayden K.-H. So, "UE-TCAM: An Ultra Efficient SRAM-based TCAM", TENCON 2015 - 2015 IEEE Region 10 Conference, pp. 1-6, Nov-2015, Macau.

  11. Manish Kumar Jaiswal, and Hayden K.-H. So, "Dual-Mode Double Precision / Two-Parallel Single Precision Floating Point Multiplier Architecture", 23rd IEEE International Conference on Very large Scale Integration (VLSI-SoC'15), pp. 213-218, 2015, Daejeon, South Korea.

  12. Manish Kumar Jaiswal, B. Sharat Chandra Varma and Hayden K.-H. So, "Architecture for Dual-Mode Quadruple Precision Floating Point Adder", 14th IEEE Computer Society Annual Symposium on VLSI (ISVLSI'15), pp.249-254 , 2015, Montpellier, France.

  13. Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan, and K. Paul,"Configurable Architecture for Double / Two-Parallel Single Precision Floating Point Division", 13th IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), pp. 332-337, 2014, Tampa, Florida, USA. DOI 10.1109/ISVLSI.2014.45

  14. Zahid Ullah, Manish Kumar Jaiswal and Ray C.C. Cheung, "Design Space Exploration of Hybrid-Partitioned TCAM (HP-TCAM)", in 23rd International Conference on Field Programmable Logic and Applications (FPL2013), Porto, Portugal, pp. 1-4, Sep-2013.

  15. Manish Kumar Jaiswal, Ray C.C. Cheung, "Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier", in The IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, Shanghai, China, pp. 369-375, May 2012.

  16. Zahid Ullah, Manish Kumar Jaiswal, Y.C.Chan and Ray C.C. Cheung, "FPGA Implementation of SRAM-based Ternary Content Addressable Memory", in The IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, pp. 376-382, May 2012. DOI 10.1109/IPDPSW.2012.47

  17. Manish Kumar Jaiswal, Ray C.C. Cheung, "Area-Efficient Architectures for Large Integer and Quadruple Precision FP Multipliers”, in The 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2012), pages 25-28, April-May 2012. DOI 10.1109/FCCM.2012.14

  18. Manish Kumar Jaiswal, Ray C.C. Cheung, "High Performance Reconfigurable Architecture for Double Precision Floating Point Division", in 8th International Symposium on Applied Reconfigurable Computing (ARC-2012), Springer LNCS, vol. 7199, pp. 302-313, 2012.

  19. Manish Kumar Jaiswal, Nitin Chandrachoodan, "A High Performance Implementation of LU Decomposition on FPGA", in 13th IEEE VLSI Design And Test Symposium (VDAT-2009), pp. 124–134, Bangalore, July. 2009.

  20. Manish Kumar Jaiswal, Nitin Chandrachoodan, "Efficient Implementation Floating-Point Reciprocator on FPGA", in 22nd IEEE International Conference on VLSI Design (VLSI-09), pp. 267-271, New-Delhi, Jan-2009.

  21. Manish Kumar Jaiswal, Nitin Chandrachoodan, "Efficient Implementation of IEEE Double-Precision Floating-Point Multiplier on FPGA", in IEEE Region 10 Colloquium and 3rd International Conference on Industrial and Information Systems (ICIIS-08), pp. 1-4, IIT-Kharagpur, Dec-2008.


Edited Books:

  1. A. B. Chong, R. G. Mishra, and Manish Kumar Jaiswal, “Reconfigurable Computing - Embedded, FPGA Based, VLSI and ASIC Designs”, HCTL Open Science and Technology Letters, June 2013, ISBN: 978-162776963-1.


Others:

  1. Manish Kumar Jaiswal, “PACoGen: Posit Arithmetic Core Generator" [Online] https://github.com/manish-kj/PACoGen, 2019.

  2. Manish Kumar Jaiswal, “Posit HDL Arithmetic" [Online] https://github.com/manish-kj/Posit-HDL-Arithmetic, 2018.

  3. Ph.D. Thesis: "Configurable Architectures for Mixed High Precision Floating Point Arithmetic", City University of Hong Kong, 2014.

  4. M.S.(By Research) Thesis:"Hardware Acceleration of Block LU Decomposition", IIT Madras, India, 2009.

  5. Internship Report: "Implementation of SSTA Components on CELL-BE Multi-Core Processor", Six month Internship, IBM INDIA Pvt. Ltd., Bangalore, India, 2008.