Today's embedded computing world has been overloaded with applications with high computational demands, in addition to being constrained by cost, footprint and battery life. Each new application is associated with custom compute requirements that need to be met with a fast time-to-market. However, designing a custom micro-architecture for every new application is expensive and time consuming. In addition, the competition-driven industry calls techniques that make systems deployable with a short concept-to-realisation time. Extracting performance from traditional sequential computing methods has reached its limits. The breakdown in the growth of performance-per-watt complemented with ever increasing transistor densities, challenges the conventional o.-the-shelf processing paradigms for the new generation embedded computing applications.
In particular, the focus of this research is to:
1. build an automated design flow to develop "just-in-time customisation" to simplify concept-to-realisation in embedded system design for diverse applications with high computational demands and stringent resource constraints.
2. develop a reusable and reconfigurable research infrastructure that provides a platform for collaborative multi-disciplinary research in India.
I am looking for bright and motivated students with an MTech (CSE or ECE) and a strong interest in Computer architecture and FPGA/VLSI design.This project is funded by Science and Engineering Research Board, Government of India.
Prospective students may write to me: p_madhura@blr.amrita.edu
Eligibility:
This is a DST funded project, hence all pre-requisite eligibility criteria as per DST guidelines have to be met. This implies all applicants should have a minimum of Masters' level degree (M.Tech/ M.S., similar)
Salary:
1st & 2nd year: 3.9 lakh/year [renewal based on annual appraisals]
3rd year: Will be considered for SRF position at a salary of 4.36 lakh/ year [subject to annual performance review]
Duration: Three years