My CV

1. Educational Qualifications

• 10/2010 - 09/2013: Doctor of Electronic Engineering at the University of Electro-Communications, Tokyo, Japan.
  • Dissertation title: "Research on a Parallel CAM-based Hardware System for Parallel Information Detection and Its Applications."
• 09/2002 - 01/2005: Master of Science in Physical Electronics, the University of Science, Vietnam National University – Ho Chi Minh City, Vietnam.
  • Thesis title: “Designing a Fixed-point 16-bit Digital Signal Processor Using FPGA Technology.”
• 09/1997 - 09/2001: Bachelor of Science in Physics, Vietnam National University – Ho Chi Minh City, Vietnam
• Other qualifications:
  • IC-CAP Agilent Certificate
  • Cadence Certificates of IC Design
  • Cadence Certificates of PCB Design
  • Certificate of the Training Program for Vietnamese Software Design and Development Engineers (VNSW), The Association for Overseas Technical Scholarships (AOTS), Japan and Information Technology Training Institute (ITTI), Vietnam
  • Certificate of Open Source Software Leader, Vietnam Ministry of Science and Technology and Center of the International Cooperation for Computerization (CICC), Japan.

2. Professional summary

• +10 years experienced in FPGA design
• +8 years experienced in PCB design
• +6 years experienced in Digital IC design and VLSI design
• +4 years experienced in SoC design
• +10 years experienced in management
• Experience with PCB design: schematics, PCB library, layout, high speed and high density multi-layer PCB, CAD/CAM, Manufacturing output
• Experience with programming on FPGA using Verilog/VHL, SoPC design, SW/HW Co-design
• Experience using Synopsys/Cadence tools and design flow: Floorplanning, Physical Synthesis, CTS, P&R, STA, Power analysis, DRC/LVS, Noise analysis, DfT, Scan insertion, ATPG
• Successful tape-out experience of multiple complex chips at 180nm, 90nm, 65nm
• Low-power flow (power gating, multi-Vt, dynamic voltage scaling, body biasing, SOTB devices)
• Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM, etc.)
• MOSFET device modeling and parameter extraction (MOS Level 1-2-3), BSIM, EKV

3. Skills of using tools

• PCB design: OrCAD, Allegro (Cadence), PADS Power PCB, Board Station, Design Architect (Mentor Graphics)
• FPGA design: Xilinx ISE, Quartus II Altera
• Custom IC design: Virtuoso, Assura, Spectre (Cadence), PrimeTime, Star-RCXT, Nanosim, Cosmoscope, HSPICE (Synopsys)
• Digital IC Design: Buildgates, SOC Encounter (Cadence), DC Compiler, IC Compiler, Formal Verification (Synopsys), Calibre, Hercules, Dracula (Mentor Graphics)
• MOSFET Parameter extraction: IC-CAP (Agilent)
• Device and Process Simulation: Atlas, Athena, Deckbuild, Tonyplot (Silvaco TCAD)
• Engineering simulation: Labview, Matlab
• Programming languages: C/C++, PEL (Parameter Extraction Language), Verilog HDL
• Operating Systems: Unix, Linux, Windows

4. Scholarships

• 10/2000: Scholarship of Fujimoto (Japan)
• 11/2001: Scholarship of Global Cybersoft .Inc (USA)
• 06/2004: Scholarship of HB7ND (New Zealand)
• 2006 – 2008: DAAD scholarship holder (Germany)
• 2010 – 2013: MEXT scholarship from the Japanese government (Japan)

5. Awards

• The Third prize of the Creativity of Science and Technology Contest, Ho Chi Minh City, 2005.
• The Best Paper Award at the IEEE International Conference of Communications and Electronics (ICCE), Hue City, Vietnam, August, 2012.

6. Exhibitions:

• International Consumer Electronics Show (CES) 2012, Las Vegas, NV, USA.
  • Search-less Information Detection (SLID) with ultra-fast DNA, Face, and Pattern Detection.
• International Consumer Electronics Show (CES) 2013, Las Vegas, NV, USA.
  • Search-less Information Detection (SLID) with ultra-fast Text, Letter, Temperature, DNA, Face, and Pattern Detection.

7. Languages

• English
• German
• Japanese

8. Employment records

• 04/2014 - now: Faculty of Electronics and Telecommunications, the University of Science Ho Chi Minh City - VNUHCM, Vietnam
  • Job description: Head of Digital Signal Processing and Embedded Systems Laboratory (DESLAB).
• 2013 - 2014: The University of Electro-Communications, Tokyo, Japan.
  • Job description: Postdoctoral researcher, VLSI design and Industry-academia-government collaboration researcher.
• 2010 – 2013: The University of Electro-Communications, Tokyo, Japan.
  • Job Description:
    • PhD. candidate at The University of Electro-Communications, Tokyo, Japan.
    • Collaborator at Advanced Original Technology Inc. (AOT), Japan.
• 2009 – 2010: Faculty of Electronics and Telecommunications, the University of Science Ho Chi Minh City - VNUHCM, Vietnam
  • Job Description: Lecturer, Execution manager of DESLAB (DSP and Embedded System Laboratory)
• 2007 – 2008: Institute for Microelectronics, Stuttgart, Germany
  • Job Description: Research assistant
  • Parameter extraction of thin film transistors under mechanical stresses using IC-CAP.
  • Device simulation using TCAD Silvaco tools
• 2006 – 2007: Faculty of Electronics and Telecommunications, the University of Science Ho Chi Minh City - VNUHCM, Vietnam
  • Job Description: Lecturer, Vice Dean 2006 - 2007
• 2003 – 2006: Faculty of Physics, Department of Electronics, the University of Science Ho Chi Minh City - VNUHCM, Vietnam
  • Job Description: Lecturer
• 2002 – 2003: Global CyberSoft VietNam Ltd.
  • Job Description: EDA Engineering
  • IC and PCB design. With Cadence and Mentor Graphics
• 2001 – 2002: Faculty of Physics, Department of Electronics, the University of Science Ho Chi Minh City - VNUHCM, Vietnam
  • Job Description: Lecturer Assistance