SoC Design Laboratory

Welcome to System-on-a-Chip Design Laboratory

We are a research group at the Department of Electronics Engineering, Konkuk University, South Korea. Our research interests include simulating and optimizing SoC accelerators for diverse computation-intensive signal processing algorithms where both algorithmic and architectural design space exploration is crucial to the performance and complexity (e.g., digital modems for WiFi and 6G cellular networks). We are currently developing a push-button style agile SoC design methodology using SystemC-TLM (Transaction-Level Modeling) based virtual prototype (virtual platform) simulators (e.g., Synopsys's Platform Architect), which helps engineers to focus on algorithm-architecture co-design rather than tedious design steps (e.g., RTL design/verification). The purpose of our in-house accelerator simulator, AccTLMSim, includes (1) optimizing hardware-software partitioning and on-chip memory-network design and (2) leveraging the efficacy of the state-of-the-art EDA tools (e.g., Mentor's Catapult HLS and Synopsys ASIP Designer). 

SoC Design Laboratory, Konkuk University

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