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Triple patterning lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in the 14nm technology node and beyond. It is necessary to consider TPL in early design stages to make the layout more TPL friendly and reduce the manufacturing cost. In this work, we propose a flow to co-optimize cell layout decomposition and detailed placement. Our cell decomposition approach can enumerate all coloring solutions with the minimum number of stitches. The experimental results show that our approach can outperform the existing work in all aspects of stitch number, half-perimeter wirelength (HPWL), and running time. We further extend our placer to consider the displacement of cells as a constraint and as an objective, respectively, which can help to preserve the quality of the input placement. Effectiveness of the extensions is verified by the experiments.
Triple patterning lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in the 14nm technology node and beyond. It is necessary to consider TPL in early design stages to make the layout more TPL friendly and reduce the manufacturing cost. In this work, we propose a flow to co-optimize cell layout decomposition and detailed placement. Our cell decomposition approach can enumerate all coloring solutions with the minimum number of stitches. The experimental results show that our approach can outperform the existing work in all aspects of stitch number, half-perimeter wirelength (HPWL), and running time. We further extend our placer to consider the displacement of cells as a constraint and as an objective, respectively, which can help to preserve the quality of the input placement. Effectiveness of the extensions is verified by the experiments.
To compare or to use these data, please cite the following paper:
To compare or to use these data, please cite the following paper:
Jian Kuang, Wing-Kai Chow and Evangeline F.Y. Young,
Jian Kuang, Wing-Kai Chow and Evangeline F.Y. Young,
"Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell Based Designs",
"Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell Based Designs",
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.4, 2016.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.4, 2016.
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