Professor
Yongjun Park
Associate Professor
Division of Computer Science and Engineering
Department of Computer Science, Department of Artificial Intelligence
Hanyang University, Seoul, Korea
EDUCATION
05/2009 – 08/2013 Ph.D. in Electrical Engineering, University of Michigan, Ann Arbor, MI
(Advised by Prof. Scott Mahlke)
09/2007 – 04/2009 M.S.E in Electrical Engineering, University of Michigan, Ann Arbor, MI
03/1999 – 02/2007 B.S. in Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea
EXPERIENCE
03/2021 - Present Associate Professor at Hanyang University, Seoul, Korea
03/2017 - 02/2021 Assistant Professor at Hanyang University, Seoul, Korea
09/2014 - 02/2017 Assistant Professor at Hongik University, Seoul, Korea
05/2013 – 08/2014 Software Architect at Intel, Santa Clara, CA
01/2002 - 01/2005 Researcher and Engineer at ALTECH (Airlink Technology), Seoul, Korea
SELECTED PUBLICATIONS (see full publications: dblp, Google Scholar )
Legion: Tailoring Grouped Neural Execution Considering Heterogeneity on Multiple Edge Devices, ICCD 2021
Convergence-Aware Neural Network Training, DAC 2020
Navigator: Dynamic Multi-kernel Scheduling to Improve GPU Performance, DAC 2020
Optimization of a GPU-based Sparse Matrix Multiplication for Large Sparse Networks, ICDE 2020
PreScaler: An Efficient System-aware Precision Scaling Framework on Heterogeneous Systems, CGO 2020
GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data Parallel Architectures, DAC 2019
Improving GPU Multitasking Efficiency using Dynamic Resource Sharing, IEEE CAL 2018
NN Compactor: Minimizing Memory and Logic Resources for Small Neural Networks, DATE 2018
Dynamic Resource Management for Efficient Utilization of Multitasking GPUs, ASPLOS 2017
A Bypass First Policy for Energy-Efficient Last Level Caches, SAMOS 2016
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs, ISCA 2016
ELF: Maximizing Memory-level Parallelism for GPUs with Coordinated Warp and Fetch Scheduling, SC 2015
Fine Grain Cache Partitioning using Per-Instruction Working Blocks, PACT 2015
Chimera: Collaborative Preemption for Multitasking on a Shared GPU. ASPLOS 2015
Enabling Efficient Alias Speculation. LCTES 2015
Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems. PACT 2013
SIMD defragmenter: efficient ILP realization on data-parallel architectures. ASPLOS 2012
Process variation in near-threshold wide SIMD architectures. DAC 2012
Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability. MICRO 2012
Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. MICRO 2009