Chip gallery

NeuFlow System-on-Chip (flipchip packaged)

Process: IBM 45nm SOI

Disclosure:

www.neuflow.org (2012)

64-PE on-chip network for coarse-grained processor array

Process: 0.13um STD-cell CMOS

Disclosure:

Pham et al. IEEE CICC 2009, Pham et al. IEEE Trans. VLSI Syst., (DOI 10.1109/TVLSI.2011.2181546)

16-PE multi-stage on-chip network for arbitrary traffic permutation

Process: 0.13um STD-cell CMOS

Disclosure:

Pham et al. IEEE Trans. VLSI Syst., (DOI 10.1109/TVLSI.2011.2181545)

5-bidirectional-port backtracking wave-pipeline NoC switch

Process: 0.18um STD-cell CMOS

Disclosure:

Pham et al. IEEE Trans. VLSI Syst., (DOI 10.1109/TVLSI.2010.2096520)