Tips for PCB Design

PCB Design

1. Remove Rooms. Project->Project Options -> Class Generation and unchecked Component Classes column [Generate Rooms].
2. Change preferences to our necessity.
   1. Design -> Board Options: Units: Metric.
   2. Tools -> Design Rule Check
      • Report Options and Stop when 10000 violations found.
      • Rules to check and Un-Routed Net unchecked. (Before to finish the design give back ti checked.
   3. Design -> Rules -> Design Rule:
      1. Electrical |Clearence | Clearence (Minimum Clearance): change to 0.15mm.
      2. Routing | Width | Width. Minimum Width (0.1mm.).
      3. Routing Via Style| Add ThruVia propertie with the following parameters:
         • uVia: Full Query: ((StartLayer = 'L1') and (StopLayer = 'L2')) or ((StartLayer = 'L2') and (StopLayer = 'L3')) or ((StartLayer = 'L8') and (StopLayer = 'L9')) or ((StartLayer = 'L9') and (StopLayer = 'L10'))
           • Via Diameter. Minimum = Maximum = Preferred = 0.25 mm.
           • Via Hole Size. Minimum = Maximum = Preferred = 0.1 mm.
         • BuriedVia: Full Query: ((StartLayer = 'L3') and (StopLayer = 'L8'))
           • Via Diameter. Minimum = Maximum = Preferred = 0.45 mm.
           • Via Hole Size. Minimum = Maximum = Preferred = 0.2 mm.
         • ThruVia: Full query: ((StartLayer = 'L1') and (StopLayer = 'L10'))
           • Via Diameter. Minimum = 0.2 mm, Maximum = 0.5 mm Preferred = 0.45 mm.
           • Via Hole Size. Minimum = 0.1 mm, Maximum = 0.25 mm, Preferred = 0.2 mm.
      4. Add properties to BuriedVia and uVia too.
   4. Design -> Rules:
   • Design rules | Manufacturing:
     • Hole to Hole Clearance: change to 0.1mm.
     • Minimum Solder Mask Silver: change to 0.1mm.
     • Silk To Solder Mask Clearence: change to 0.1mm.
     • Silk To Silk Clearence: change to 0.1mm.
   • Design rules | Placement:
     • Component Clearence: change Minimum Vertical and Horizontal Clearence and to 0.2mm.
3. Add stackup Layer: Design -> Layer Stack Manager.
4. DXP -> Preferences -> PCB Editor -> Defaults -> Via to configure your default via. Diameter [Simple], Hole Size[ 0.2mm], Diameter [.45 mm.] Specific expansion value [-10mm] to mask all vias.
5. Create your board outline [Mechanical 5].
6. Place your through hole components, mount holes and your main components, and finally print it out in scale 1:1 to check everything it's ok.
7. Firts of all place all your vias.
8. Start the layout with the memories.
9. Route differential pairs:
   1. In the schematic, you can to define TAG_NAME_P and TAG_NAME_N, for the positive a negative differential pairs and add property: Place -> Directives -> Differential Pair to the lines.
   2. Design -> Update PCB.
   3. Design -> Rules -> Routing -> Differential Pairs Routing:
      • Min Gap = Min Clearance = Min Width = 0.15mm.
      • Min Gap = Max Gap = Prefered Gap = 0.15mm.
10. Guide Design Document: http://www.ampro.com/tmp/COMExpressPnP_DG_09.pdf
11. Guide Design for stack up layer: hdi _layer_stackups_for_large_dense_pcbs.pdf
12. Use custom grids for BGAs. It's the way tu put vias in the middle of 4 balls.
13. Power planes have to meet the 20H rule. Power plane deeper then ground plane for improve EMI issues.
14. Top and Bottom show you work. Be carefully with this two layers.
15. Put in Assembly Drawing pin one mark (a dot).
16. If you put text in the top. Put Top Solder, for eliminate the solder mask in the words. Looks fine.
17. Place order:
    1. Place memories and processor.
    2. Placement order in BGAS. We have to start in the middle of the BGA:
       • Power, decoupling capacitors.
       • Precise resistors/capacitors. The highest important components when doing the placement: decoupling capacitors and reference resistors. SHORT CONNECTION, WIDE TRACK (LOW IMPEDANCE CONNECTION).
       • Series resistors (e.g.: 22R) near the output.
       • Series capacitor, e.g. in PCI express bus. The capacitor are near the output (PCIE_TXN and PCIE_TXP).
       • Crystals should be placed near the pins and if it's possible in the same layer (side). Connection as short as possible.
       • Resistors of bootstrap, pull-up and pull-down, near CPU to avoid large tracks.
       • We continue with the next difficult BGA chip. Use the advices in step 2.
       • Next step Buses: PCI, SATA,
       • Use the same topology in the same buses. Very Important for High Speed Design. Group the signal with the same topology.
       • At this stage of the design layout don't worry about perfect tracks, because you redrawing them very times. The goal is connected all the pins in the similar way. Always use wider track for power supplies and power rails, because the default width track it's 0.1 mm. At this stage, do not worry about small violations, fix big violations.
       • Differential pair routing.
       • Connect Long Length Buses, then High pin number buses.
       • Local connections - Power supplies, Small circuits, Connectors. Tip: Pick up a corner and work systematically.
       • Local connections - Analog areas.
       • Connect rest of unconnected signals (1 wire nets, LEDs, ...).
       • Connect Power nets.
       • clear DRC.
18. Add layer Manufacturing Notes. Work with 2.5 mm snap in this layer.
19. Add Gerber files description:
    • *.GTO - Top Overlay
    • *.GTP - Top Paste
    • *.GTS - Top Solder
    • *.GTL - L1 (Signal)
    • *.G1 - L2 (Signal)
    • *.G2 - L3 (Signal)
    • *.GP1 - L4 (Plane)
    • *.GP2 - L5 (Plane)
    • *.G3 - L6 (Signal)
    • *.G4 - L7 (Signal)
    • *.GP3 - L8 (Plane)
    • *.GP4 - L9 (Plane)
    • *.G5 - L10 (Signal)
    • *.G6 - L11 (Signal)
    • *.GBL - L12 (Signal)
    • *.GBS - Bottom Solder
    • *.GBP - Bottom Paste
    • *.GBO - Bottom Overlay
    • *.GM2 - Mechanical Drawing
    • *.GM4 - Manufacturing Notes
    • *.GM5 - Board Outline
20. Add layer stack table in layer Manufacturing Notes in Mechanical layer 4: Place -> Layer Stack Table.
21. Add layer Border Out Layer in Mechanical layer 5. Border Out Layer.
22. Add layer Mechanical Drawing in Mechanical layer 6. Mechanical Drawing.
23. Add Gerber files and NC Drill files to Fabrication Outputs in our Output Job. [milimeters and 4:4 format]
24. Add Mechanical Drawings to Assembly Outputs in Output job file. [Print to PDF Creator. Print scaled].
25. Add Assembly Drawings to Assembly Outputs in Output job file. [Print to PDF Creator. Fit to page].
26. Add Simple Boom and Bill of material to Report Outputs in Output job file.
27. Add Schematics Outputs to Documentation Outputs in Output job file.

!!! IMPORTANT !!! Release Document for Altium Designer.txt

1. Right Click on the project -> Compile PCB project. I confirm, the project compiles with no errors: YourIntials [DAY-MONTH-YEAR]
2. Run Design -> Update PCB Document: I confirm, there are no differences between Schematic and PCB: YourIntials [DAY-MONTH-YEAR]
3. Impedance: I confirm, I have updated and check track width/gap to match required impedance (e.g 55 OHMs): YourIntials [DAY-MONTH-YEAR]
4. Polygon Action -> Repour All: I confirm, all polygons have been repoured: YourIntials [DAY-MONTH-YEAR]
5. Run Tools -> Design Rule Check -> Run Design Rule Check: I confirm, I have checked Design Rule Output File: YourIntials [DAY-MONTH-YEAR]
6. Gerber check: I confirm, I have copied and visually checked gerber files placed in \PCB Manufacturing\Gerber Output\ YourIntials [DAY-MONTH-YEAR]
7. Other files: I confirm, I have copied and checked files placed in subdirectories: YourIntials [DAY-MONTH-YEAR] = OGF [02-01-2014]

and copy all documents generated to Fedevel directory Template->Released Files->ClientName->ProjectName->VxIx:

Step 1 - PCB Manufacturing.

Step 2 - Board Assembly.

Step 3 - Firmware.

Step 4 - 3D.

Step 5 - Schematic.

Step 6 - Source Files.