Gururaj Saileshwar 

I am a 3rd year PhD Student in School of Electrical and Computer Engineering at Georgia Tech, USA,  working with Prof. Moinuddin Qureshi. I work at the intersection of Computer Architecture & Hardware Security. I am currently investigating problems in cache & main-memory security - designing secure memory systems that incur low performance & energy overheads. 

I have had the good fortune of interning in multiple industry research labs. In Summer-2018, I interned at Intel Labs - Security & Privacy Research in Hillsboro, Oregon. At Intel, I worked on software memory safety - reducing overheads of detecting software memory-bugs like buffer-overflows. In Summer-2017, I interned at Arm Research in Austin, Texas in the Memory Systems group. My work explored low-overhead hardware-integrity solutions for memory systems.

I received my B.Tech & M.Tech in Electrical Engineering at Indian Institute of Technology - Bombay, India in 2014, with a Minor Degree in Computer Science and Engineering.  In what seems like a past life, I also worked as a Management Consultant at Boston Consulting Group in Mumbai, India.
You can check out my CV here or learn more about me from my Linkedin profile.


    • Our paper "Morphable Counters: Enabling Compact Integrity-Trees for Low-Overhead Secure Memories" is accepted at MICRO-2018[Paper]
    • Our paper "SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories" is accepted at HPCA-2018! [Paper]