Publication

Google Scholar: http://scholar.google.com/citations?user=PoyUjb4AAAAJ&hl=en

DBLP: http://www.informatik.uni-trier.de/~ley/db/indices/a-tree/l/Lee:Jeong=Gun.html

1.   [ME] "A Study on Basic Gate Implementation of Asynchronous Circuits Using Binary Decision Diagrams," Jeong-Gun Lee, Master Thesis, Gwangju Institute of Science and Technology, Nov. 1997.

2.   [PhD] "Issues of Asynchronous Distributed Control and Variable Delay Computation for High Performance System Design," Jeong-Gun Lee, PhD Dissertation, Gwangju Institute of Science and Technology, Nov. 2004.

3.   [ME] "Power Consumption and Energy Efficiency Performance Evaluation of GPU for Beamforming in Medical Image Processing," Rafael, Master Thesis, Hallym University, 2014

4.   [ME] "Design Space Exploration of a SW Beamformer on GPUs and Its Performance Prediction," Phung Thi Yen, Master Thesis, Hallym University, 2014

5.   [ME] "Ultrasound Beamforming Design Using OpenCL and Its Performance Evaluation and Comparison on Multiple Manycore Platforms," Hana Park, Master Thesis, Hallym University, 2014

6.   [PhD] "Analysis and Design of a Digital Switching Noise Suppression Technique based on Multi-Phase Clocking in SoCs," Nguyen Van Toan, PhD Dissertation, Hallym University, 2018

7.   [PhD] "A Carry Chain Based All-Digital MFC and All-Digital VLRO Designs on an FPGA," Dam Minh Tung, PhD Dissertation, Hallym University, 2018

8.   [ME] "FCL-Net: 온디바이스를 위한 필터 조합 학습 네트워크 (FCL-Net: Filter Combination Learning Network for on-devices)," Jaemin Jeong, Master Thesis, Hallym University, 2020

9.   [ME] "수면 단계 분류 자동화를 위한 딥러닝 모델 연구 (A Study on Deep Learning Models for Automatic Sleep Stage Classification)," Dong-Young Kim, Master Thesis, Hallym University, 2020

10.   [PhD] "A study on performance optimization of sleep stage classification deep learning model using imaged biosignal data," Yunhee Woo, PhD Dissertation, Hallym University, 2022

[1] "Automatic Process-Oriented Asynchronous Control Unit Generation from Control Data Flow Graphs," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A, No.8, pp.2014-2028, August 2001.

[2] "Test Generation for SI Circuits with Undetectable Faults from STG," Eunjung Oh, Jeong-Gun Lee, Ho-Yong Choi and Dong-Ik Lee, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 6, pages 1506-1514, June 2001.

[3] "A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains," Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A No.12, pp.3166-3173, December 2004

[4] "Procedural Constraints in the Extended RBAC and the Coloured Petri Net Modeling," Wook Shin, Jeong-Gun Lee, Hong Kook Kim, and Kouichi Sakurai, IEICE Transactions on Fundamentals, Special Section on Cryptography and Information Security, Vol.E88-A No.1 pp.327-330, January 2005.

[5] "Instruction Level Redundant Number Computations for Fast Data Intensive Processing in Asynchronous Processors," Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee, Journal of Systems Architecture, Vol 51/3, pp 151-164, Elsevier Press, March 2005.

[6] "A Low Latency Asynchronous FIFO Combining a Wave Pipeline with Handshake Scheme," Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee and Kiseon Kim, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A(4):1031-1037 April 2005.

[7] "Differential Value Encoding for Delay Insensitive Handshake," Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Sun Jhang, and Dong-Soo Har, IEICE Transactions on Information and Systems, Vol.E88-D No.7 pp.1437-1444, July 2005.

[8] "Low Latency Four-flop Synchronizer with the Handshake Interface," Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim, IEICE Transactions on Information and Systems, Vol.E88-D No.7 pp.1460-1463, July 2005.

[9] "Design of a Mutated Adder and Its Optimization Using ILP Formulation," Jeong-Gun Lee, Jeong-A Lee, Suk-Jin Kim, and Kiseon Kim, IEICE Transactions on Information and Systems, Vol.E88-D No.7 pp.1506-1508 July 2005.

[10] "Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion," Eun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Son Jhang, Jeong-A Lee, and Dong-Soo Har, IEICE Transactions on Electronics Vol.E88-C, No.12, pp.2395-2399, Nov. 2005.

[11] "Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions," Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, and Dong-Soo Har, The Journal of VLSI Signal Processing, Springer Press, Volume 46, No. 2-3, pp. 133-151, March 2007.

[12] "Intelligent sensor node based a low power ECG monitoring system," Min Zeng, Jeong-Gun Lee, Goang-Seog Choi, and Jeong-A Lee, IEICE Electron. Express, Vol. 6, No. 9, pp.560-565, May 2009.

[13] "Exploration of Power-Delay Tradeoffs with Heterogeneous Adders by Integer Linear Programming," Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee, In Journal of Circuits, Systems, and Computers, Vol. 18, No. 4 PP.787–800, June 2009.

[14] "A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques," Jeong-Gun Lee, Wook Shin, Suk-Jin Kim, and Eungu Jung, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E93-A, No.6,  pp.1215-1225, June 2010.

[15] "472 MHz Throughput Asynchronous FIFO Design On a  Virtex-5 FPGA Device," Jeong-Gun Lee, Myeong-Hoon Oh, Deok-Young Lee and Young-Woong Ko, IEICE ELEX, May 2011.

[16] "Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme," Jeong-A Lee, Zahid Ali Siddiqui, Natarajan Somasundaram, and Jeong-Gun Lee, In Journal of Semiconductor Technology and Science, Vol. 13, No. 5, October 2013.

[18] "A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking," Jeong-Gun Lee, IEICE Transactions on Electronics, Vol.E97-C,No.12,pp.1158-1161, Dec. 2014

[19] "Deduplication TAR Scheme Using User-Level File System," Young Woong Ko, Min-Ja Kim, Jeong-Gun Lee, Chuck Yoo, IEICE Transactions 97-D(8), 2174-2177, 2014

[20] "Zero latency synchronization scheme using prediction and avoidance of synchronization failure in heterochronous clock domains," Sung-Gun Song, Myeong-Hoon Oh, Jeong-Gun Lee, Sung-Mo Park, In Journal of Semiconductor Technology and Science, Volume 15, Number 2, April 2015

[21] "Design Space Exploration of SW Beamformer on GPU," Thi Yen Phuong and Jeong-Gun Lee, in Concurrency and Computation: Practice and Experience, Volume 27, Issue 7, pages 1718–1733, May 2015 (Ranked R2 in JCR)

[22] "A Performance-Aware Yield Analysis and Optimization of Manycore Architectures," Jeong-Gun Lee and Sanghoon Kwak, Computers & Electrical Engineering,  Volume 54, August 2016, Pages 40–52, (Impact Factor: 1.084, 24/51 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE) ( Published Version ) [Funded by NSF2015]

[24] "Design of a Clockless MSP430 Core Using Mixed Asynchronous Design Flow," Ziho Shin, Myeong-Hoon Oh, Jeong-Gun Lee, Hag Young Kim, and Young Woo Kim, IEICE Electronics Express, March 31, 2017 [Funded by NSF2015]

[25] "Exploring the Impacts of Optimization Strategies on Performance, Power/Energy Consumption of a GPU based Parallel Reduction," Thi Yen Phuong, Deok-Young Lee and Jeong-Gun Lee, Journal of Central South University, Volume 24, Issue 11, pp 2624–2637, Nov. 2017 [Funded by NSF2015]

[26] "Measurements of Metastability in MUTEX on an FPGA," Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee, IEICE Electronic Express, Vol.15, No.1, pp. 1–11, Jan. 2018 [Funded by NSF2015] 

[28] "A Carry Chain Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation," Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee, in Journal of Circuits, Systems, and Computers, Vol. 28, Issue 1, Jan. 2019. [Funded by NSF2015]

[29] "EM Emanation Exploration in FPGA-based Digital Design," Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee, Journal of Central South University, Volume 26, Issue 1, pp 158−167 Jan. 2019. [Funded by NSF2018]

[30] "A High-Resolution and Glitch-Free All-Digital Variable Length Ring Oscillator Design on an FPGA," Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee, in Computers & Electrical Engineering, An International Journal, Volume 74, March 2019, Pages 149-163, 2019. (Impact Factor: 2.189, R2 in JCR)[Funded by NSF2018]

[31] "Immunity Characterization of I/O Supply Voltage Scaled and Fault Tolerant Circuits against EMI," Nguyen Van Toan, Dam Minh Tung, Jungmin So, Jeong-Gun Lee, Advances in Electrical and Computer Engineering, May, 2019 [Funded by NSF2018 and Hallym University Research Fund]

[33] "G-DCF: Improving System Spectral Efficiency through Concurrent Transmissions in Wireless LANs," Ayinebyona Eliab, Yonghwi Kim, Joosang Lee, Jeong-Gun Lee and Jungmin So, Wireless Communications and Mobile Computing 2019.

[34] "In-Situ Timing Detector Based Two Cycles Adaptive Frequency Scaling System on FPGAs," Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee, in Journal of Circuits, Systems, and Computers, scheduled to Vol 29 No... 6, May 2020 (JCSC) [Funded by NSF2018]

[36] "An One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA," Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee, MDPI Electronics, 9 / 633, April, 2020. (Impact Factor: 1.764 (2018), Funded by NSF2018 and Hallym University Fund) (LINK)

[37] "Filter Combination Learning for Convolutional Neural Network," Jaemin Jeong, Ji-Ho Cho and Jeong-Gun Lee, in ICT Express, Vol. 7, Issue 1, March, 2021  [Funded by NSF2018] (Impact Factor: 4.317 )

[38] "Zero-Keep Filter Pruning for Energy/Power Efficient Deep Neural Networks," Yunhee Woo, Dongyoung Kim, Jaemin Jeong and Young-Woong Ko and Jeong-Gun Lee (Y.-W. Ko and J.-G. Lee are Co-Corresponding Author), Electronics 2021, 10(11), 1238. [Funded by NSF2018]  (Impact Factor: 2.397)

(* Revision *)

(* Submitted *)

[42] "Frequency Classification Using Deep Learning," Jaemin Jeong and Jeong-Gun Lee, Submitted.

[43] "Analysis of Transformer’s Attention Behavior in Sleep Stage Classification and Limiting it to Improve Performance," Dongyoung Kim, Younghoon Na, Dong-Kyu Kim* and Jeong-Gun Lee*, Submitted

(* In Preparation *)

[44] "Error-Resilient Inference with an Error-Aware Activation Function in a Deep Neural Network,"  Jeong-Gun Lee, Nguyen Van Toan, Young-Woong Ko and Jungmin So, In Preparation.

[45] "Model Compression," Jaemin Jeong and Jeong-Gun Lee, In Preparation.

[46] "Impact of Visually Represented Bio-signals in Deep Learning based Sleep Stage Classification," Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Wonsook Lee, Dong-Kyu Kim and Jeong-Gun Lee

[1] "Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization," Jeong-Gun Lee, Euiseok Kim, Jeong-A Lee, Eunok Paek, In Proc. of Ninth Asia-Pacific Computer Systems Architecture Conference (LNCS - Volume 3189 / 2004), pp. 582 - 595, Sep., 2004.

[2] "A Design Method for Heterogeneous Adders," Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac, In Proc. International Conference on Embedded Software and Systems (Lecture Notes in Computer Science) 2007.

[3] "An Asymptotic Performance/Energy Analysis and Optimization of Multi-Core Architectures," Jeong-Gun Lee, Eungu Jung, and Wook Shin, in 10th International Conference on Distributed Computing and Networking - LNCS, January 3-6, 2009 [Submitted Version(Long Version) - PDF]

[4] "Data Deduplication System for Supporting Multi-Mode," Ho Min Jung, Won Vien Park, Wan Yeon Lee, Jeong Gun Lee and Young Woong Ko,  Lecture Notes in Artificial Intelligent (Lecture Notes in Computer Science, Volume 6591/2011, pp.78-87), ACIIDS, Daegu, Korea, April 20-22, 2011.

[5] "Energy Efficient File Transfer Mechanism Using Deduplication Scheme," Ho Min Jung, Sung Woon Kang, Jin Kim, Wan Yeon Lee, Jeong-Gun Lee, Young Woong Ko, pp. 421-428, ICHIT (Lecture Notes in Computer Science, 2011, Volume 6935/2011, pp.421-428), Daejeon, Korea, September 22-24, 2011.

[6] "Monitoring and Feedback Tools for Realtime Workloads for Xen Virtual Machine," Byung Ki Kim, Jae Hyeok Jang, Kyung Woo Hur, Jeong Gun Lee and Young Woong Ko, Lecture Notes in Electrical Engineering, 1, Volume 120, Proceedings of the International Conference on IT Convergence and Security 2011, Part 3, Pages 151-161, December 14 -16,  Suwon, 2011

[7] "A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration," Hasan Baig, Jeong-Gun Lee and Jeong-A Lee, ADVANCES IN AUTOMATION AND ROBOTICS, VOL. 2, (Lecture Notes in Electrical Engineering, Volume 123), pp.281-290, Dec. 2011

[8] "Low Latency Scheduling on Multi BOOST Environment", Byung Ki Kim, Jeong Gun Lee, Seon Woo Lee, and Young Woong Ko, , ICHIT, AUG, 2012.

· Book Chapter - Springer

[1] "Minimizing Scheduling Delay for Multimedia in Xen Hypervisor," Jeong-Gun Lee, Kyung Woo Hur and Young Woong Ko, Communications in Computer and Information Science, 1, Volume 199, Advanced Communication and Networking, Pages 96-108, August 15 - 17 2011.

[2] "Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study," Seung-Joon Lee, Deok-Young Lee, Young Woong Ko and Jeong-Gun Lee, in Communications in Computer and Information Science, August 2012.

[1] "Automatic Distributed Asynchronous Control Circuit Generation From Data Flow Graph for Asynchronous High-Level Synthesis," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of 2000 IEEE International Symposium on Circuits and Systems, pp.II-49-II-52, May, 2000.

[2] [ASYNC] "Automatic Process-Oriented Control Circuit Generation For Asynchronous High-Level Synthesis," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp.104-113, 2000.

[3] [ASP-DAC] "Imprecise Data Computation for High Performance Asynchronous Processors," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of IEEE/ACM ASP-DAC'2001, pp.261-266, Feb., 2001.

[4] [ARVLSI] "Building a Distributed Asynchronous Control Unit Through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of 2001 IEEE Conference on Advanced Research in VLSI, pp.2-15, Mar., 2001.

[5] "A Simulator for Performance Evaluation of Asynchronous Systems," Sang-Ik Choi, Jeong-Gun Lee, Dong-Ik Lee and Seok-Hwan Yoon, In Proceedings of International Conference on VLSI, pp.66-71, Jun., 2002.

[6] "Dynamic Clock Frequency Scaling in Globally Asynchronous and Locally Synchronous Systems," Suk-Jin Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of 2002 Conference of Asia-Pacific System on a Chip, pp. 114-119, 2002. Best Paper Awarded

[7] [ASP-DAC] "Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units," Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura and Takashi Nanya, In Proceedings of IEEE/ACM ASP-DAC'2003, pp.261-266, Feb., 2003.

[8] [DATE] "Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units," Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura and Takashi Nanya, In Proceedings of IEEE/ACM DATE'2003 - Design, Automation and Test in Europe Conference and Exhibition, pp.276-281, Mar., 2003.

[9] "Synthesis of a Single-Dual-Single Wrapper for a Generalized Synchronous Variable Computation Time Arithmetic Unit," Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura and Takashi Nanya, In Proceedings of IWLS'2003 - International Workshop on Logic and Synthesis, pp.29-35, May, 2003.

[10] "Implementation of a Generalized Synchronous Variable Computation Time Arithmetic Unit with a Single-Dual-Single Wrapper," Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura and Takashi Nanya, In Proceedings of ITC-CSCC'2003 - International Technical Conference on Circuits/Systems, Computers and Communications, pp.1075-1078, July, 2003.

[11] "Dynamic Clock Frequency Scaling in GALS on-chip Network Systems," Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim, In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 6C2L-4-1 ~ 6C2L-4-4, Jul., 2004.

[12] "Differential Value Encoding for Two-Phase 1-of-N Delay Insensitive Handshake Protocol in GALS Systems," Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Sun Jhang, Dong-Soo Har, In Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2004.

[13] "Two-Phase 1-of-N Delay Insensitive Handshake Protocol using Differential Value Encoding for SoC," Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Sun Jhang, Dong-Soo Har, In Proc. International Scientific-Practical Conference on Communication (ISPC-COMM), Aug., 2004.

[14] "A parallel flop synchronizer for asynchronous domains," Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim, In Proceedings of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Aug, 2004.

[15] "Handshake-Wave Combined Approach with Runtime Reconfiguration for Designing a Low Latency Asynchronous FIFO," Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, Euiseok Kim, Kiseon Kim, In Proceedings of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Aug, 2004.

[16] "Design of a Mutated Adder and its Optimization Using ILP Formulation," Jeong-Gun Lee, Jeong-A Lee, Suk-Jin Kim, Seong-Yong Ahn, Kiseon Kim, In Proceedings of the Work in Progress Session of the EUROMICRO /DSD conference event in Rennes (France), August 31 - September3, 2004.

[17] "Expanding Design Space of Adder Architecture for Better Time-Area Trade-offs," Jeong-Gun Lee, Jeong-A Lee, Suk-Jin Kim, Kiseon Kim, In Proceedings of International System On Chip Conference (ISOCC), Oct., 2004.

[18] [GLVLSI]  "High Performance Asynchronous On-Chip Bus with Multiple Issue and Out-of-Order/In-Order Completion," Eun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har, In Proceedings of IEEE/ACM Great Lakes Symposium on VLSI (GLVLSI) 2005.

[19] "Reconfigurable Co-synthesis System Architecture," Ji-han Park, Sang-Hoon Kwak, Jeong-Gun Lee, Jeong-A Lee, and Dong-soo Har, in Proceedings of International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC'2005), pp. 445-446, Jul. 2005

[20] "Implementation of Asynchronous Reorder Buffer for Asynchronous On-Chip Bus," Eun-Gu Jung, Jeong-Gun Lee, Hamza Fraz, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har, In Proceedings of the 7-th International Symposium on Signals, Circuits and Systems (ISSCS), Romania on 14-15 July 2005.

[21] "Better Area-Time Tradeoffs in an Expanded Design Space of Adder Architecture by Parameterizing Bit-width of Various Carry Propagated Sub-adder-blocks," Jeong-Gun Lee Jeong-A Lee, Deok-Young Lee, IEEE International Workshop on System on Chip (IWSOC), Dec. Cairo, 2006.

[22] [NOC] "Implications of Rent’s Rule for NoC Design and Its Fault-Tolerance," Dan Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon Moore, In IEEE Symposium on Network on Chip, 2007.

[23] "Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip," Jeong-Gun Lee and Eungu Jung, International Conference on Computer Design (CDES), Jul. 2008.

[24] "Design of Heterogeneous Adders Based on Power-delay Tradeoffs," Sanghoon Kwak, Dongsoo Har, Jeong-Gun Lee, Jeong-A Lee, The Fifth IEEE International Symposium on Embedded Computing ( SEC 2008), Oct. 2008.

[25] "Asymptotic Performance Analysis and Optimization of Resource-Constrained Multi-Core Architectures," Jeong-Gun Lee, Eungu Jung, and Dong-Wook Lee, in Proceedings of The IEEE International Conference on Microelectronics (ICM), 14-17 December, 2008.

[26] "The Use of Fair Y-Sim for Optimizing Mapping Set Selection in Hardware / Software Co-Design," Olufemi Adeluyi , Eunok Kim, Jeong-Gun Lee, and Jeong-A Lee, in Proceedings of IEEE International SoC Design Conference (ISOCC), Nov. 24-25, 2008.

[27] "Optimal Position Searching for Automated Malware Signature Extraction," Yangseo Choi, Jintae Oh, Jeong-Gun Lee, Jaecheol Ryou, in Proceedings of The 13th IEEE International Symposium on Consumer Electronics, Mielparque-Kyoto, Kyoto, Japan, May 25-28, 2009.

[28] "FPGA based Asynchronous FIFO Designs and Its Performance Analysis," Seung-Joon Lee, Sang-Hoon Kwak, Jeong-Gun Lee, The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2011), June 19 ~ 22, Gyeongju, Korea, 2011.

[29] [Invited] "An On-Node Intelligence based Energy Efficient ECG Monitoring System," Min Zeng, Il-Yong Chung, Jeong-A Lee, Jeong-Gun Lee, International Conference on ICT Convergence 2011 (ICTC 2011), Seoul, Korea, Sep. 2011.

[30] "Low Area and High Speed SHA-1 Implementation," Eun-Gu Jung, Daewan Han, Jeong-Gun Lee, International SoC Design Conference (ISOCC 2011), Jeju, Nov.  2011.

[31] "GPU-Based Real Time Ultrasound Beamformer," Thi Yen Phuong, Jeong-Gun Lee, GPU Technology Conference (GTC 2014), Poster Session, Mar.  San Jose, 2014.

[32] [HiPC] "Software Based Ultrasound B-mode/Beamforming Optimization on GPU and its Performance Prediction," Thi Yen Phuong, Jeong-Gun Lee, In 21th IEEE International Conference on High Performance Computing, 2014. [acceptance rate: 49/216 = 23%]

[33] "Impact of Optimization Strategies on Power and Energy Consumption on GPUs," Thi Yen Phuong and Jeong-Gun Lee, International Conference on Green and Human Information Technology (ICGHIT), Danang, Vietnam, Feb. 2015.

[34] "Design of a Multi-Frequency Clocking Circuit on an FPGA and Analysis of Its EMI Impact," Nguyen Van Toan, Minh-Tung Dam, and Jeong-Gun Lee, in Topical Symposiums on IC-EMC of APEMC, 18-21 May, Shenzhen China, 2016

[35] "The Impact of IO Supply Voltage Levels on Radiated EMI," Minh-Tung Dam, Nguyen Van Toan, and Jeong-Gun Lee, in Topical Symposiums on IC-EMC of APEMC, 18-21 May, Shenzhen China, 2016

[36] "A Globally Asynchronous Locally Synchronous Design with Clock Phase Modulation for Conducted EMI Reduction" Nguyen Van Toan, Minh-Tung Dam, and Jeong-Gun Lee, 2017 International Conference on Electonics, Information, and Communication, Jan. 2017.

[37] (I2MTC) "Exploring the Current Consumption of an Intel Edison Module for IoT Applications" Minh-Tung Dam, Nguyen Van Toan, and Jeong-Gun Lee, In the 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC 2017), May 2017.

[38] "Exploring the Impact of Multi-Frequency Clocking and GALS Design on Power Supply Noises," Nguyen Van Toan, Minh-Tung Dam, and Jeong-Gun Lee, In APEMC 2017

[39] [MSWCAS] "Energy-Efficient and High Performance 2-Phase Asynchronous Micropipelines", Nguyen Van Toan, Minh-Tung Dam, and Jeong-Gun Lee, In 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), June 2017.

[40] "In-Situ Detector-Based AFS System on an FPGA," Minh-Tung Dam, Nguyen Van Toan, and Jeong-Gun Lee, In the IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips, April 2018.

[41] "A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction," Nguyen Van Toan, Minh-Tung Dam, and Jeong-Gun Lee, in the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2018), Chengdu, China, October 26-30, 2018. (Excellent Presentation Award)

[42] "Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on an FPGAs," Nguyen Van Toan and Jeong-Gun Lee, Accepted in the IEEE International System-on-Chip Conference (SOCC), Sep., 2019

[43] "Filter Combination Learning for Convolutional Neural Network," Jaemin Jeong, Dongyoung Kim, Yunhee Woo and Jeong-Gun Lee, The 11th International Conference on ICT Convergence, October 21-23, 2020

[44] "Zero-Keep Filter Pruning for Energy Efficient Deep Neural Network," Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Youngwoong Ko and Jeong-Gun Lee, The 11th International Conference on ICT Convergence, October 21-23, 2020

[45] "Sleep Stage Classification for Inter-institutional Transfer Learning," Dongyoung Kim, Yunhee Woo, Jaemin Jeong, Dong-Kyu Kim* and Jeong-Gun Lee*,  (* Co-corresponding authors), The 12th International Conference on ICT Convergence, October 20-22, Jeju, Korea, 2021

[46] "Image-based Sleep Stage Classification Model for Multi-Institutional Dataset," Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Dong-Kyu Kim* and Jeong-Gun Lee*,  (* Co-corresponding authors), The 12th International Conference on ICT Convergence, October 20-22, Jeju, Korea, 2021

[47] "Shaped Pruning for Efficient Memory Addressing in DNN Accelerators," Yunhee Woo, Dongyoung Kim, Jaemin Jeong and Jeong-Gun Lee, IEEE/IEE The Sixth International Conference On Consumer Electronics (ICCE) Asia, Nov. 1~3, Gangwon, Korea, 2021

[48] "Entropy-Based Model Generalization for Sleep Stage Classification," Dongyoung Kim, Yunhee Woo, Younghoon Na, Jeong-Gun Lee* and Dong-Kyu Kim*, (* Co-corresponding authors), The 13th International Conference on ICT Convergence, October, Jeju, Korea, 2022

[49] "Evaluation of OSA Patient Sleep Stage Classification Performance Using a Multi-Channel PSG Dataset," Younghoon Na, Dongyoung Kim, Dong-Kyu Kim* and Jeong-Gun Lee*, (* Co-corresponding authors), IEEE/IEE The Sixth International Conference On Consumer Electronics (ICCE) Asia, Oct. 26~28, Gangwon, Korea, 2022

[50] "Standardized Image-Based Polysomnography Database and Deep Learning Algorithm for Sleep Stage Classification" Jaemin Jeong, Wonhyuck Yoon, Jeong-Gun Lee, Dongyoung Kim, Yunhee Woo, Dong-Kyu Kim, Hyun-Woo Shin, ICCV 2023 Workshop on Computer Vision for Automated Medical Diagnosis , (Poster Presentation), Oct. 2, Paris, France, 2023

[51] "Error-Resilient Inference With an Error-Aware Activation Function in a Deep Neural Network", Jeong-Gun Lee and Dongyoung Kim,  ICEIC 2024, JAN. 28-31, Taiwan, 2024

[52] "Improved Generalization From Limiting Attention in a Transformer for Sleep Stage Classification", Dongyoung Kim, Dongkyu Kim and Jeong-Gun Lee, ICEIC 2024, JAN. 28-31, Taiwan, 2024

(* In preparation *)

[1] "A Low Latency Asynchronous FIFO Combining a Wave Pipeline with Handshake Scheme," Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, 2004 GIST / Tokyo University Joint Workshop on Asynchronous System Design, University of Tokyo, Tokyo, Japan, 2004.

[2] "Issues of Asynchronous Distributed Control and Variable Delay Computation for High Performance System Design," Jeong-Gun Lee, GIST / Univ. of Osaka Joint Workshop, Jeju Island, South Korea, Jan. 2005.

[3] "Selecting a Timing Regime for On-Chip Networks," Robert Mullins, Jeong-Gun Lee, Simon Moore, 17th UK Asynchronous Circuit Forum, University of Southampton, United Kingdom, 5-6 Sep. 2005.

[4] "Towards a Communication-Centric Design Methodology," A. Banerjee, R. Francis, J. Lee, J. May, S.W. Moore and R. D. Mullins, First Workshop on Future Interconnects and Network on Chip, Munich, Mar. 2006.

[1] "Asynchronous Controller Generation Method," Dong-Ik Lee, Euiseok Kim and Jeong-Gun Lee, Registered in US patent, Patent No: US 6,594,815, July 15, 2003.

[2] "Data Transmitting Circuit and Method Based On Differential Value Data Encoding," Eun-Gu Jung, Jeong-Gun Lee, Dong-Soo Har, US Patent No: US 7,170,431, 30 January 2007.

[3] "Mixed-type Adder Comprising Multiple Sub-adders, Each of Which Has Different Carry Propagation Scheme," Jeong-A Lee, Kiseon Kim, Jeong-Gun Lee, and Suk-Jin Kim, US Patent 7,562,107 B2, Jul. 14, 2009

[4] "Hybrid adder comprising multiple sub-adders, each of which uses a different carry propagation scheme," Jeong-A Lee, Kiseon Kim, Jeong-Gun Lee, and Suk-Jin Kim, EUROPEAN PATENT : EP 1 650 647 B1, Aug. 5, 2009

[1] "Reachability Characterization for Bounded Petri Nets Based on Unfoldings," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, SOFTWARE ENGINEERING REVIEW, pp.67-75, Mar. 2000.

[2] "Pragmatic Reachability Analysis of Bounded Petri Nets Based on Unfoldings," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, Journal of KISS : Computer Systems and Theory, Vol. 27, No. 6, pp.599-607, Jun. 2000.

[3] "Deriving a Distributed Asynchronous Control Unit through Automatic Derivation of Asynchronous Finite State Machines Based on the Process-Oriented Method," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, Journal of KISS : Computer Systems and Theory, Vol. 28, No. 7, pp.356-372, Jul. 2001.

[4] "Automatic STG Derivation with Consideration of Special Properties of STG Based Asynchronous Logic Synthesis," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, Journal of KIPS, Vol. 9-A, No. 3, pp.351-352, Sep. 2001.

[5] "SLEDS: A System-Level Event-Driven Simulator for Asynchronous Microprocessors," Sang-Ik Choi, Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee, Journal of KISS : Computer Systems and Theory, Vol. 29, No. 1, pp.42-55, 2002.

[6] "Extending the Design Space of Adder Architectures and Its Optimization Using Integer Linear Programming," Deok-Young Lee, Jeong-A Lee, Jeong-Gun Lee and Sang-Min Rhee, KIPS Transactions: Technology Education, Vol. 1, No. 1, pp.64-70, June 2006.

[7] "정수 선형 프로그래밍을 이용한 혼합 가산기 구조의 최적 설계," Deok-Young Lee, Jeong-Gun Lee, Jeong-A Lee and Sang-Min Rhee, Journal of KISS : Computer Systems and Theory, Vol. 34, No. 7/8, pp.327-336, Aug. 2007.

[8] "μC/OS-II 운영체제환경을 고려한 SDL 명세로부터의 내장형 C 코드 자동 생성," Sang-Hoon Kwak and Jeong-Gun Lee, Journal of the Korea Society of Computer and Information, pp. 46-55, May 2008.

[9] "고성능/저전력 3D 기하 연산을 위한 오프라인 CORDIC 벡터회전 알고리즘," Eunok Kim, Jeong-Gun Lee, Jeong-A Lee, Journal of KISS:Computing Practices and Letters, No. 14, Vol. 8, pp.763-767, Nov. 2008.

[10] "안전한 인터넷 뱅킹을 위한 트랜잭션 서명기법에 관한 연구," Hyung-Jin Lim, Jeong-Gun Lee, Moonseong Kim, Journal of Korean Society for Internet Information, pp.129-135, Dec. 2008.

[11] "저전력 SoC을 위한 동적 주파수 제어 시스템의 FPGA 프로토타입 설계," Eungu Jung, Jeong-Gun Lee, Journal of KISS: Computing Practices and Letters, Nov. 2009

[12] "향상된 연산시간, 회로면적, 소비전력의 절충관계를 위한 혼합가산기 기반 CORDIC," Byeong-Seok Lee, Jeong-Gun Lee, Jeong-A Lee, Journal of the Korea Society of Computer and Information, Vol.15, No.2, pp. 9-18, Feb. 2010.

[13] "Power-Delay Product Optimization of Heterogeneous Adder Using Integer Linear Programming," Sang-Hoon Kwak, Jeong-Gun Lee, and Jeong-A Lee, Journal of the Korea Society of Computer and Information, Vol.15, No.10, pp. 1-9, Oct. 2010.

[14] "FPGA 장치 기반의 비동기식 FIFO 구조 설계 및 성능 평가," Seung-Joon Lee, Young-Woong Ko, Jeong-Gun Lee, Journal of the Korea Society of Computer and Information, Vol.15, No.10, pp. 1-9, Oct. 2011.

[15] "Accurate and Energy Efficient ECG Analysis Method for ECG Monitoring System", Min Zeng, Jeong-Gun Lee, Il-Yong Chung, Jeong-A Lee, 한국통신학회논문지 '12-05 Vol.37C No.05, May, 2012

[16] "비동기식 순차 및 병행 제어 회로의 직접 합성 규칙 (Direct Synthesis Rule for Asynchronous Sequencing and Concurrency Control Circuits)," 박하나, 이정근, 한국정보기술학회논문지 제11권 제8호, pp.1-8, 2013

[17] "비동기식 프로세서 설계 기법을 통한 저전압 동작 특성 분석과 전자기파 방사량 측정 분석," 오명훈, 김학영, 이정근, 한국정보기술학회논문지 제12권 제2호, 2014

[18] "디지털 FPGA 칩의 전자파 방출에 대한 설계공간탐색 및 분석," 이덕영, 이정근, 한국정보기술학회 논문지, 14권 8호, 8월, 2016

[19] "실시간 응용을 위한 혼합형 다중 객체 추적 시스템의 구현," 우윤희, 최권택, 이정근, 한국정보기술학회 논문지, 17권 11호, 2018

[20] "FPGA 내부 고속 캐리 체인 회로를 이용한 다중-주파수 클록 회로 설계 및 Tradeoff 분석," 이정근, 이덕영, 한국정보기술학회 논문지, Vol.19, No.1, pp. 71-78, 1월 2021

[1] "Implementability Checking and Basic Gate Synthesis of Speed-Independent Circuits Using BDD," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of Formal Method Workshop'1997, pp.44-54, 1997.

[2] "Basic Gate Level Logic Synthesis of Speed-Independent Circuit using Binary Deicision Diagram," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of IEEK Fall Conference, pp.1136-1139, 1997.

[3] "Asynchronous Circuit Initialization Using BDD," Soo-Hyun Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IEEK Summer Conference, pages 887-890, Jun,1998.

[4] "High Level Simulation of Asynchronous Circuit on Parallel Processing Environment," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of IEEK'99 CAD & VLSI Design Conference, pp. 72-77, 1999.

[5] "Testing for Speed-Independent Asynchronous Circuits Using the Self-Checking Property," Eunjung Oh, Jeong-Gun Lee, Dong-Ik Lee and Ho-Yong Choi, In Proceedings of IEEK Fall Conference, Vol. 22, No. 2, pp. 384 - 387, 1999.

[6] "Pragmatic Reachability Analysis of Bounded Petri Nets on Unfoldings," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of Formal Method Workshop'2000, pp. 165-171, 2000.

[7] "Automatic Control Circuit Generation from Data Flow Graph for Asynchronous High-Level Synthesis," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IDEC Conference 2000, pp.61-64, Feb., 2000.

[8] "Back Carry Collapsing Adder Design for High-Performance Asynchronous System," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of IDEC Conference 2000, pp.95-98, Feb., 2000.

[9] "Imprecise Data Computation for High Performance Asynchronous Processors," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of KISS Computer System Group Fall Conference, pp.88-93, 2000.

[10] "Asynchronous Linear Pipeline Dynamics and Its Application to Efficient Buffer Allocation Algorithm," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of IEEK Summer Conference, pp.109-112, 2002.

[11] "Design of a Synchronous Control Unit for a Datapath with Variable Delay Arithmetic Units," Euiseok Kim Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IEEK Summer Conference, pp.321-324, 2002.

[12] "Synthesis of Asynchronous Circuits from C Language Using Syntax Directed Translation," Sang-Hoon Kwak, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IEEK Summer Conference, pp.353-356, 2002.

[13] "Deriving an Optimized Synchronous Control Unit for a Variable Delay Datapath," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IDEC Summer Conference 2002, pp.143-146, 2002.

[14] "Buffer Allocation Optimization for Asynchronous Linear Pipelines using Performance Evaluation and Simulation Annealing," Jeong-Gun Lee, Euiseok Kim and Dong-Ik Lee, In Proceedings of SoC Design Conference, 2002.

[15] "Implementation of Distributed Synchronous Control Units for Maximizing Utilization Ratio of Variable Computation Time Arithmetic," Euiseok Kim, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of SoC Design Conference, 2002.

[16] "Two-Phase 1-of-N Data Encoding for GALS," Eun-Gu Jung, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of SoC Design Conference, 2003.

[17] "Two-Phase 1-of-N Delay Insensitive Handshake Protocol using Differential Value Encoding for System-on-Chip," Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Sun Jhang, Dong-Soo Har, In Proceedings of Fall Conference of Korea Communication Society, 2004.

[18] "Low Latency Asynchronous FIFO Design of Adopting Wave Pipelining for SoC Interconnection," Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, Euiseok Kim and Kiseon Kim, In Proceedings of CNU IDEC SoC Workshop, pp. 49-53, August 2004.

[19] "Optimum Core Partitioning for High-Performance Multi-Core Processor Design," Jeong-Gun Lee, In Proceedings of KISS Symposium, June, 2008.

[20] "CORDIC Based Off-line Vector Rotation Algorithm for High-Performance and Low-Power 3D Geometry Operations," Eunok Kim, Jeong-Gun Lee, Jeong-A Lee, In Proceedings of KCC, June, 2008. - Selected Paper.

[21] "ARM 프로세서 하에서의 코드 최적화 전략에 대한 성능 평가 (Performance Evaluation of Code Optimization Strategies for ARM Processors)," Kwang-Won Choi, Ju-Teak Sun, Jeong-Gun Lee,  in Proceedings of KIPS Fall Conference, 2009.

[22] "파일 유사도를 이용한 에너지 효율적인 파일 전송 기법," 정호민, 강성운, 이정근, 고영웅, 한국정보과학회, 2011 한국 컴퓨터 학술발표논문집 제38권 제1호(B) pp. 373-376, 2011.6

[23] "중복제거 TAR 기법을 적용한 백업 시스템," 강성운, 정호민, 이정근, 고영웅, 한국정보과학회, 2011 한국 컴퓨터 학술발표논문집 제38권 제1호(A) pp. 539-542, 2011.6  

[24] "Xen 가상 머신에서 연성 실시간 스케줄러 구현," 허경우, 이정근, 고영웅, 한국정보기술학회 2011년도 ICT 스마트기술 워크숍 및 하계종합학술, 대학생논문 경진대회논문집 pp. 256-262, 2011.5 

[25] "비동기식 회로 설계 기술 동향," 오명훈, 이정근, 김성남, 김성운, 대한전자공학회 하계 학술대회, 제주 2011

[26] "FPGA 장치 기반의 비동기식 회로설계 기법에 대한 분석," 이승준, 고영웅, 이덕영, 이정근, 대한전자공학회 하계 학술대회, 제주 2011

[27] "CRC64해시를 이용한 에너지 효율적인 파일 전송 기법 설계 및 구현," 정호민, 강성운, 이정근, 고영웅,  한국정보처리학회 춘계 학술발표논문집, 2011. 5.

[28] "데이터 중복 제거 기반의 디스크 아카이브 시스템 설계 및 구현," 강성운, 정호민, 고영웅, 이정근, 한국정보처리학회 춘계 학술발표논문집, 2011. 5. (우수논문상)

[29] "FPGA 장치 기반 Asynchronous MIPS 프로세서 설계," 이승준, 이정근, 곽상훈, 한국정보과학회/한국정보처리학회 공동 학술 심포지움, 2012. 6.

[30] "FPGA 기반의 GALS 네트워크-온-칩 아키텍쳐 설계," 곽상훈, 김강훈, 이정근, 한국정보과학회/한국정보처리학회 공동 학술 심포지움, 2012. 6.

[31] "FPGA를 이용한 비동기식 회로 설계 방식의 저전압 동작 및 전자기파 방사 특성 실측,"  오명훈, 박찬호, 김학영, 이정근, 대한전자공학회 하계종합학술대회, 7월, 2013,

[32] "OpenCL을 이용한 초음파 빔포밍 설계 및 CUDA 성능비교 (Design of Ultrasound Beamforming Using OpenCL and Its Performance Comparison with CUDA)," 박하나(Ha-Na Park), 이정근(Jeon-Gun Lee), 대한전자공학회 학술대회 논문집, Vol.2014 No.6, pp.1103-1106, 2014

[33] "GPU기반B-mode초음파영상처리구현시에크럭주파수변이에따른성능/전력/에너지평가", 퐁티옌, 이정근, 대한전자공학회 하계종합학술대회, 6월 21일(일)~23일(화), 2015

[34] "A High-Resolution Supply Voltage Sensor Design and Its Performance Evaluations on an FPGA," Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee, 한국정보과학회, 한국정보과학회 학술발표논문집, pp. 103-105, 6. 2017. (최우수 논문상:Best Paper Award)

[35] "Evaluation an EMI Reduction of a Multi-Frequency Clocking Circuit Utilizing Carry Chains on an FPGAs," Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee, 한국정보과학회, 한국정보과학회 학술발표논문집, pp. 115-117, 6. 2017.

[36] "A Design of an Error Prediction Circuit for Late Transitions Detection on an FPGA," 담민텅, 뉴엔반토안, 이정근, 제12회 한국정보과학회/ 한국빅데이터학회 공동학술 심포지엄, 2018.

[37] "딥-뉴럴 네트워크의 파라미터 최적화: MNIST 사례분석," 김민정, 임병준, 임승현, 정재민, 이종학, 이정근, 대한전자공학회 추계학술대회, 2018.

[38] "효율적인 딥러닝 학습 위한 이미지 보강 설계공간 탐색," 정재민, 김동영, 우윤희,한국정보과학회·한국빅데이터학회 공동학술 심포지엄, 2019.

[39] "딥러닝 CAM 기반 해석-가능한 영상 가시화 오픈소스 소프트웨어 도구 개발," 정재민, 함서은, 손주현, 이정근, 제30회 신호처리합동학술대회 논문집, 대한전자공학회, 9월(24-25), 2020.

[40] "실시간 수면 단계 분류를 위한 Single-epoch 모델 성능 평가," 오승훈, 김동영, 이정근, JCCI 2023 (제33회 통신정보 합동학술대회), 4월26-38, 여수, 2023

[41] "노이즈 데이터가 포함된 감정 분류에서의 RNN기반 모델의 견고성 평가," 허태훈,김동영,이정근, JCCI 2023 (제33회 통신정보 합동학술대회), 4월26-38, 여수, 2023

[1] "Asynchronous Control Circuit Generation Method," Dong-Ik Lee, Euiseok Kim and Jeong-Gun Lee, KR Patent Number 10-0345009, July, 4, 2002.

[2] "Data Transmitting Circuit and Method Based on Differential Value Data Encoding," Eun-Gu Jung, Jeong-Gun Lee, Dong-Soo Har, KR Patent No: 10-0574767, 21 April 2006.

[3] "Mixed-type Adder Comprising Multiple Sub-adders, Each of Which Has Different Carry Propagation Scheme," Jeong-A Lee, Kiseon Kim, Jeong-Gun Lee, and Suk-Jin Kim, KR Patent No: 10-0714316, 26 April, 2007.

[4] "확장형 오류검출코드 생성기, 그 생성기를 구비한 자가검사 룩업테이블 및 확장형 오류검출코드 생성방법", 이정아;소마순다람, 나타르잔;이정근, 등록 10-1267894-0000 (등록일자: 2013.05.21)

[5] "비동기 클럭을 가지는 파이프라인 회로 장치," 등록 10-1621760 (2016.05.11)

[6] "다중 주파수 클럭을 가지는 파이프라인 회로 장치," 등록10-1621761 (2016.05.11)

[7] "헬스테인먼트 운영관리 시스템 및 그 방법", 특허등록:10-2017-0010599, 2018년 11월

[8] "인공지능 모델의 필터 변환을 위한 전자 장치의 제어 방법 및 프로그램," 특허등록 제 10-2429804 호 (2022.08.02)

[9] "기계학습모델 공유 또는 판매를 위한 시스템 및 시스템의 동작 방법," 특허등록 제 10-2453673 호 (2022.10.06)

[10] "다채널의 생체 신호들을 포함하는 이미지를 기반으로 수면 단계를 분류하는 전자 장치, 및 수면 단계 분류 방법," 특허등록 제 10-2526181 호 (2023.04. 21)

[11] "인공지능 모델의 파라미터 저장을 위한 필터 조합 학습 네트워크 시스템의 제어 방법, 장치 및 프로그램," 특허등록 제 10-2544220 호 (2023.06.12)

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